
CHAPTER 1 INTRODUCTION
User’s Manual U17716EJ2V0UD
20
(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits
× 16 bits → 32 bits) and a barrel shifter (32
bits), help accelerate complex processing.
(b) Bus control unit (BCU)
The BCU controls the internal bus.
(c) ROM
This is flash memory that is mapped from address 00000000H.
During instruction fetch, ROM/flash memory can be accessed from the CPU in 1-clock cycles.
The
internal ROM capacity and area differ as follows depending on the product.
Part Number
Internal ROM Capacity
Internal ROM Area
μPD70F3713
64 KB (flash memory)
xn000000H to xn00FFFFH
μPD70F3714
128 KB (flash memory)
xn000000H to xn01FFFFH
Remark
n = xx11B
(d) RAM
This is a 6 KB internal RAM that is mapped to the addresses xnFFD800H to xnFFEFFFH.
During instruction fetch or data access, data can be accessed from the CPU in 1-clock cycles.
Remark
n = xx11B
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (INTP0 to INTP6) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiple-interrupt servicing control can be performed.
(f) Clock generator (CG)
The clock generator includes two basic operation modes: PLL mode (fixed to multiplication by eight) and
clock-through mode. It generates four types of clocks (fXX, fXX/2, fXX/4, fXX/8), and supplies one of them as
the operating clock for the CPU (fCPU).
(g) Timer/counter
This unit incorporates one 16-bit interval timer M (TMM) channel, two 16-bit timer/event counter Q (TMQ)
channels, and four 16-bit timer/event counter P (TMP) channels, and can measure pulse interval widths or
frequency, enable an inverter function for motor control, and output a programmable pulse.
(h) Watchdog timer (WDT)
A watchdog timer is equipped to detect program loops, system abnormalities, etc.
It generates a non-maskable interrupt request signal (INTWDT) or internal reset signal (WDTRES) after an
overflow occurs.