
CHAPTER 18 ELECTRICAL SPECIFICATIONS
782
User’s Manual U14492EJ5V0UD
(8) CSI timing (2/2)
(b)
Slave mode
(T
A
= –40 to
+
85
°
C:
μ
PD703116, 703116(A), 70F3116, 70F3116(A),
T
A
= –40 to
+
110
°
C:
μ
PD703116(A1), 70F3116(A1),
V
DD3
= CV
DD
= 3.0 to 3.6 V, V
DD5
= 5 V
±
0.5 V, V
SS3
= V
SS5
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle
<66>
t
CYSK1
Input
200
ns
SCKn high-level width
<67>
t
WSK1H
Input
90
ns
SCKn low-level width
<68>
t
WSK1L
Input
90
ns
SIn setup time (to SCKn
↑
)
<69>
t
SSISK
50
ns
SIn hold time (from SCKn
↑
)
<70>
t
HSKSI
50
ns
SOn output delay time (from SCKn
↓
)
<71>
t
DSKSO
55
ns
SOn output hold time (from SCKn
↑
)
<72>
t
HSKSO
t
WSK1H
ns
Remark
n = 0, 1
Remarks 1.
The broken lines indicate high impedance.
2.
n = 0, 1
<66>
<68>
<67>
<69>
<70>
<71>
<72>
SIn
(input)
SOn
(output)
SCKn
(I/O)
Output data
Input data