參數(shù)資料
型號: UPD703130GC-8EU
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 11/72頁
文件大小: 601K
代理商: UPD703130GC-8EU
Preliminary Data Sheet U15390EJ1V0DS
11
μ
PD703130
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows
the various circuit types using partially abridged diagrams.
When connecting to V
DD
or V
SS
via a resistor, a resistance value in the range of 1 to 10 k
is recommended.
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin
I/O Circuit Type
Recommended Connection of Unused Pins
P00/TO100
P02/TCLR10
P04/INTP100/DMARQ0 to
P07/INTP103/DMARQ3
P10/TO110
P12/TCLR11
P14/INTP110/DMAAK0 to
P17/INTP113/DMAAK3
5
Input:
Output:
Independently connect to HV
DD
or V
SS
via a resistor
Leave open
P20/NMI
2
Connect directly to V
SS
P22/TXD0/SO0
P23/RXD0/SI0
P24/SCK0
P25/TXD1/SO1
P26/RXD1/SI1
P27/SCK1
P33/TI13
P34/INTP130
P50/D8 to P57/D15
P60/A16 to P67/A23
5
Input:
Output:
Independently connect to HV
DD
or V
SS
via a resistor
Leave open
P70/ANI0 to P73/ANI3
9
Connect directly to V
SS
P80/CS0, to P83/CS3/RAS3
P84/CS4/RAS4/IOWR,
P85/CS5/RAS5/IORD
P90/LCAS/LWR
P91/UCAS/UWR
P92/RD
P93/WE
P94/BCYST
P95/OE
P96/HLDAK
P97/HLDRQ
P100/TO120
P102/TCLR12
5
Input:
Output:
Independently connect to HV
DD
or V
SS
via a resistor
Leave open
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