- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384043 > UPD4990AC (NEC Corp.) SERIAL I/O CALENDAR & CLOCK CMOS LSI PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD4990AC |
| 廠商： | NEC Corp. |
| 英文描述： | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| 中文描述： | 串行I / O日歷 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 129K |
| 代理商： | UPD4990AC |
7
μ
PD4990A
Command input
(1) 3-bit binary code input: C
2
, C
1
, C
0
(2) 4-bit serial transfer command input: C
3
', C
2
', C
1
', C
0
'
Number of commands
C
2
, C
1
, C
0
C'
3
, C'
2
, C'
1
, C'
0
Register control
4
4
TP select
3
8
TP control
0
3
Test mode set
1
1
Commands (C
3
', C
2
', C
1
', C
0
' commands are made effective only when [C
2
, C
1
, C
0
] = [1, 1, 1].)
(1) Register control
[C
2
, C
1
, C
0
] / [C
3
', C
2
', C
1
', C
0
']
°
Register Hold Mode
[C
2
, C
1
, C
0
]
The 40-bit shift register is held. The year function is ineffective.
[C
3
', C
2
', C
1
', C
0
']
The 48-bit shift register is held.
The command register is not held.
* The DATA OUT output frequency is 1 Hz.
°
Register Shift Mode
[C
2
, C
1
, C
0
]
The 40-bit shift register data can be shifted. The year function is ineffective.
[C
3
', C
2
', C
1
', C
0
']
Data in 52-bit shift registers (including command registers) can be shifted. For command register, data can
be always shifted using the serial command transfer mode.
* The DATA OUT output is LSB data from the shift register.
°
Time Set and Counter Hold Mode
[C
2
, C
1
, C
0
]
Data is transferred from the 40-bit shift register to the time counter. The year function is ineffective.
[C
3
', C
2
', C
1
', C
0
']
Data is transferred from the 48-bit shift register to the time counter.
* This command is used to reset the last 10-15 of 15 Stage Binary Divider and holds the time counter.
15 Stage Binary Divider resetting and time counter release are executed by the following:
[C2, C1, C0] = [0, 0, 0] [0, 0, 1] [0, 1, 1] [C3', C2', C1', C0'] = [0, 0, 0, 0] [0, 0, 0, 1] [0, 0, 1, 1]
The time setting accuracy is
±
15.625 ms.
The DATA OUT pin outputs LSB data (0 or 1) from the shift register.
After this command is executed, the 40-/48-bit shift register is held and data cannot be shifted.
°
Time Read Mode
[C
2
, C
1
, C
0
]
Data is transferred from the time-counter to the 40-bit shift register. The year function is ineffective.
[C
3
', C
2
', C
1
', C
0
']
Data is transferred from the time counter to the 48-bit shift register.
* The DATA OUT pin output is a 1 Hz frequency.
After this command is executed, the 40-/48-bit shift register is held and data cannot be shifted.
[0, 0, 0] / [0, 0, 0, 0]
[0, 0, 1] / [0, 0, 0, 1]
[0, 1, 0] / [0, 0, 1, 0]
[0, 1, 1] / [0, 0, 1, 1]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD4990AG | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| UPD63210 | 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO |
| UPD63210GT | 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO |
| UPD63210L | 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO |
| UPD63210LGT | 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4990AG-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4991ACX-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD4992CX-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD50256CP15 | 制造商:HIT 功能描述:50256 HITACHI'86 SMT N9F8A |
| UPD50256CP-15 | 制造商:HIT 功能描述:50256 HITACHI'86 SMT N9F8A |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。