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參數(shù)資料
| 型號： | UPD4990AC |
| 廠商： | NEC Corp. |
| 英文描述： | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| 中文描述： | 串行I / O日歷 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 129K |
| 代理商： | UPD4990AC |
13
μ
PD4990A
DATA INPUT/OUTPUT TIMING DIAGRAM
Figure 4.
Note:
Reading-in timing of CPU (Trailing edge of CLK).
TIMING DIAGRAM OF DATA INPUT AND OUTPUT
Figure 5.
CLK
DATA
IN
DATA
OUT
OUT
ENBL
Written-in data LSB ("H")
appears at output.
'86
November 25 (Sat.)
2 hours 23 minutes
49 seconds.
'70
July 16 (Sun.)
2 hours 24 minutes
35 seconds.
"1" year "10" year
"1" s.
"1" min.
"10" s.
"1" year "10" year
"1" s.
"1" min.
"10" s.
INPUT
TIMING
OUTPUT
TIMING
0 1 2 3 4 5 6 7 8 9 1011
4041424344454647
Command (C
2
, C
1
, C
0
) is set to (1, 1, 1).
Command (C
3
', C
2
', C
0
') is set to [0001] (Register Shift Mode).
CS = "H"
V
IH
V
IL
V
IH
CLK
DATA OUT
DATA IN
V
IL
V
OH
V
OL
t
dC-O
t
dC-O
t
DSU
t
DHLD
:
:
:
1 s MAX. (R
L
= 33 k
, C
L
= 25 pF)
1 s MIN.
1 s MIN.
t
DHLD
t
DSU
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