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參數(shù)資料
| 型號： | UPD485505G-25 |
| 廠商： | NEC Corp. |
| 英文描述： | LINE BUFFER 5K-WORD BY 8-BIT |
| 中文描述： | 行緩沖區(qū)5K - Word的8位 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 174K |
| 代理商： | UPD485505G-25 |
μ
PD485505
6
Data Sheet M10059EJ7V0DS00
Operation-related Restriction
Following restriction exists to read data written in a write cycle.
Read the written data after an elapse of 1/2 write cycle + t
WAR
since the write cycle ends (see
Figure 2.1
).
If t
WAR
is not satisfied, the output data may undefined.
Figure 2.1 Delay Bits Restriction Timing Chart
Remark
This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR
signals.
0
1
2
3
0
1
2
0
1
2
3
0
1
2
3
WCK
RCK
D
IN
D
OUT
1/2 write cycle
t
WAR
t
AC
High
impedance
High impedance
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