參數資料
型號: UPD485505G-25
廠商: NEC Corp.
英文描述: LINE BUFFER 5K-WORD BY 8-BIT
中文描述: 行緩沖區(qū)5K - Word的8位
文件頁數: 14/20頁
文件大小: 174K
代理商: UPD485505G-25
μ
PD485505
14
Data Sheet M10059EJ7V0DS00
4.2 n Bit Delay
It is possible to make delay read from the write data with the
μ
PD485505.
(1) Perform a reset operation in the cycle proportionate to the delay length. (
Figure 4.3
)
(2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length. (
Figure 4.4
)
(3) Shift the address by disabling RE for the period proportionate to the delay length. (
Figure 4.5
)
n bit: Delay bits from write cycle to read cycle correspond to a same address cell.
Restrictions
Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer
to
2. Operation Mode Operation-related Restriction
.
Cycle time
MIN.
MAX.
25 ns
21 bits
5,048 bits
35 ns
15 bits
5,048 bits
Figure 4.3 n-Bit Delay Line Timing Chart (1)
t
WCK
t
RCK
Cycle 0
Cycle 1
Cycle 2
1 H
(n Cycles)
Cycle n–1
2 H
(n Cycles)
t
WCW
t
RCW
t
WCP
t
RCP
t
RS
t
RH
t
DH
t
DS
(0)
(1)
(n–2)
(n–1)
(0’)
(1’)
t
DS
t
DH
t
OH
t
AC
(0)
(1)
(2’)
(3’)
(2)
(3)
WCK/RCK
(Input)
D
IN
(Input)
D
OUT
(Output)
t
RS
t
RH
(2)
RSTW /
RSTR
(Input)
Cycle 0’
Cycle 0
Write
Read
Cycle 1’
Cycle 1
Cycle 2’
Cycle 2
Cycle 3’
Cycle 3
t
WAR
Remark
RE, WE = “L” level
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