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參數(shù)資料
| 型號： | UPD4564441 |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 6400位同步DRAM 4銀行，LVTTL |
| 文件頁數(shù)： | 35/85頁 |
| 文件大小： | 919K |
| 代理商： | UPD4564441 |
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Data Sheet E0149N10
35
μ
PD4564441, 4564841, 4564163
C Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
/CAS Grade
Maximum
Unit
Notes
latency
×
4
×
8
×
16
Operating current
I
CC1
Burst length = 1,
CL = 2
-A80
75
80
90
mA
1
t
RC
≥
t
RC (MIN.)
, Io = 0 mA,
-A10
65
70
80
One bank active
-A10B
60
65
70
CL = 3
-A80
80
85
115
-A10
70
75
90
-A10B
70
75
90
Precharge standby current
I
CC2
P
CKE
≤
V
IL (MAX.)
, t
CK
= 15 ns
1
1
1
mA
in power down mode
I
CC2
PS CKE
≤
V
IL (MAX.)
, t
CK
=
∞
1
1
1
Precharge standby current
in non power down mode
I
CC2
N
CKE
≥
V
IH (MIN.)
, t
CK
= 15 ns, /CS
≥
V
IH (MIN.)
,
Input signals are changed one time during 30 ns.
20
20
20
mA
I
CC2
NS
CKE
≥
V
IH (MIN.)
, t
CK
=
∞
,
Input signals are stable.
6
6
6
Active standby current
I
CC3
P
CKE
≤
V
IL (MAX.)
, t
CK
= 15 ns
5
5
5
mA
in power down mode
I
CC3
PS CKE
≤
V
IL (MAX.)
, t
CK
=
∞
4
4
4
Active standby current
in non power down mode
I
CC3
N
CKE
≥
V
IH (MIN.)
, t
CK
= 15 ns, /CS
≥
V
IH (MIN.)
,
Input signals are changed one time during 30 ns.
25
25
25
mA
I
CC3
NS
CKE
≥
V
IH (MIN.)
, t
CK
=
∞
,
Input signals are stable.
15
15
15
Operating current
I
CC4
t
CK
≥
t
CK (MIN.)
, Io = 0 mA,
CL = 2
-A80
90
105
165
mA
2
(Burst mode)
All banks active
-A10
70
80
130
-A10B
65
70
110
CL = 3
-A80
105
125
195
-A10
90
105
165
-A10B
90
105
165
CBR (auto) refresh current
I
CC5
t
RC
≥
t
RC (MIN.)
CL = 2
-A80
130
130
130
mA
3
-A10
130
130
130
-A10B
105
105
105
CL = 3
-A80
135
135
135
-A10
135
135
135
-A10B
115
115
115
Self refresh current
I
CC6
CKE
≤
0.2 V
1
1
1
mA
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured condition that addresses are changed only one time during t
CK (MIN.)
.
2.
I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured condition that addresses are changed only one time during t
CK (MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
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