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參數(shù)資料
| 型號： | UPD4564441 |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 6400位同步DRAM 4銀行，LVTTL |
| 文件頁數(shù)： | 11/85頁 |
| 文件大小： | 919K |
| 代理商： | UPD4564441 |
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Data Sheet E0149N10
11
μ
PD4564441, 4564841, 4564163
Fig.1 Mode register set command
CLK
/WE
/CAS
/RAS
/CS
CKE
H
Add
A10
A12, A13
Fig.2 Row address strobe and
bank activate command
CLK
/WE
/CAS
/RAS
/CS
CKE
H
Add
A10
A12, A13
(Bank select)
Row
Row
Fig.3 Precharge command
CLK
/WE
/CAS
/RAS
/CS
CKE
H
Add
A10
A12, A13
(Bank select)
(Precharge select)
2. Commands
Mode register set command
(/CS, /RAS, /CAS, /WE = Low)
The
μ
PD4564xxx has a mode register that defines how the device
operates. In this command, A0 through A13 are the data input pins.
After power on, the mode register set command must be executed to
initialize the device.
The mode register can be set only when all banks are in idle state.
During 2 CLK (t
RSC
) following this command, the
μ
PD4564xxx cannot
accept any other commands.
Activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The
μ
PD4564xxx has four banks, each with 4,096 rows.
This command activates the bank selected by A12 and A13 (BS) and a
row address selected by A0 through A11.
This command corresponds to a conventional DRAM’s /RAS falling.
Precharge command
(/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by
A12 and A13 (BS). When A10 is High, all banks are precharged,
regardless of A12 and A13. When A10 is Low, only the bank selected
by A12 and A13 is precharged.
After this command, the
μ
PD4564xxx can’t accept the activate
command to the precharging bank during t
RP
(precharge to activate
command period).
This command corresponds to a conventional DRAM’s /RAS rising.
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