參數(shù)資料
型號(hào)： UPD45128163G5-A10T-9JF
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
中文描述： 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝： PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 16/86頁(yè)
文件大?。?/td> 774K
代理商： UPD45128163G5-A10T-9JF
Data Sheet E0348N10 (Ver. 1.0)
16
μ
PD45128163-T
(3/3)
Notes
Current state
/CS /RAS /CAS /WE
Address
Command
Action
Write recovering
H
×
×
×
×
DESL
Nop
→
Enter row active after t
DPL
L
H
H
H
×
NOP
Nop
→
Enter row active after t
DPL
L
H
H
L
×
BST
Nop
→
Enter row active after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
8
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write recovering
H
×
×
×
×
DESL
Nop
→
Enter precharge after t
DPL
with auto precharge
L
H
H
H
×
NOP
Nop
→
Enter precharge after t
DPL
L
H
H
L
×
BST
Nop
→
Enter precharge after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3, 8
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Refreshing
H
×
×
×
×
DESL
Nop
→
Enter idle after t
RC
L
H
H
×
×
NOP/BST
Nop
→
Enter idle after t
RC
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
H
×
×
ACT/PRE/PALL
ILLEGAL
L
L
L
×
×
REF/SELF/MRS
ILLEGAL
Mode register
H
×
×
×
×
DESL
Nop
→
Enter idle after t
RSC
accessing
L
H
H
H
×
NOP
Nop
→
Enter idle after t
RSC
L
H
H
L
×
BST
ILLEGAL
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
×
×
×
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Notes 1.
All entries assume that CKE was active (High level) during the preceding clock cycle.
If all banks are idle, and CKE is inactive (Low level),
μ
PD45128xxx will enter Power down mode.
All input buffers except CKE will be disabled.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
If all banks are idle, and CKE is inactive (Low level),
μ
PD45128xxx will enter Self refresh mode. All input
buffers except CKE will be disabled.
Illegal if t
RCD
is not satisfied.
Illegal if t
RAS
is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Must mask preceding data which don't satisfy t
DPL
.
10.
Illegal if t
RRD
is not satisfied.
2.
3.
4.
Remark
H = High level, L = Low level,
×
= High or Low level (Don’t care), V = Valid data
5.
6.
7.
8.
9.
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