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參數(shù)資料
| 型號： | UPD444004L |
| 廠商： | NEC Corp. |
| 英文描述： | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
| 中文描述： | 4分位CMOS快速靜態(tài)存儲器100萬字的4位 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 100K |
| 代理商： | UPD444004L |
9
μ
PD444004L
Data Sheet M14427EJ4V0DS
Write Cycle
Parameter
Symbol
-A8
-A10
-A12
Unit
Notes
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
8
10
12
ns
/CS to end of write
t
CW
6
7
8
ns
Address valid to end of write
t
AW
6
7
8
ns
Write pulse width
t
WP
6
7
8
ns
Data valid to end of write
t
DW
4
5
6
ns
Data hold time
t
DH
0
0
0
ns
Address setup time
t
AS
0
0
0
ns
Write recovery time
t
WR
0
0
0
ns
/WE to output in high impedance
t
WHZ
4
5
6
ns
1, 2
Output active from end of write
t
OW
3
3
3
ns
Notes
1.
Transition is measured at
±
200 mV from steady-state voltage with the output load shown in
Figure 2
.
2.
These parameters are periodically sampled and not 100% tested.
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
WP
t
AS
t
WR
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input / Output)
t
DH
t
WHZ
t
AW
High
impe-
dance
High
impe-
dance
t
OW
Indefinite data out
Data in
Indefinite data out
t
DW
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1.
Write operation is done during the overlap time of a low level /CS and a low level /WE.
2.
When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
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相關代理商/技術參數(shù) |
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|---|---|
| UPD444004LE-12-A | 制造商:Renesas Electronics Corporation 功能描述: |
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| UPD444008LLE-A10(A) | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD444008LLE-A12-A | 制造商:Renesas Electronics 功能描述:12ns 3.3V Cut Tape |
| UPD444012AGY-B70X-MJH(A) | 制造商:Renesas Electronics Corporation 功能描述: |
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