參數(shù)資料
型號(hào)： UPD4443362
廠商： NEC Corp.
英文描述： 4M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 128K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
中文描述： 4分位CMOS同步快速靜態(tài)內(nèi)存128K的，Word的36位HSTL接口/寄存器間/晚寫
文件頁(yè)數(shù)： 1/16頁(yè)
文件大?。?/td> 113K
代理商： UPD4443362
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confirm that this is the latest version.
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availability and additional information.
2000
MOS INTEGRATED CIRCUIT
μ
PD4443362
4M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
128K-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
DATA SHEET
Document No. M14439EJ2V0DS00 (2nd edition)
Date Published February 2001 NS CP(K)
Printed in Japan
The mark
#
shows major revised points.
Description
The
μ
PD4443362 is a 131,072 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The
μ
PD4443362 is suitable for applications which require synchronous operation, high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
The
μ
PD4443362 is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low
capacitive loading.
Features
Fully synchronous operation
HSTL Input / Output levels
Fast clock access time : 3.8 ns (133 MHz)
Asynchronous output enable control : /G
Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
Common I/O using three-state outputs
Internally self-timed write cycle
Late write with 1 dead cycle between Read-Write
3.3 V (Chip) / 1.5 V (I/O) supply
100-pin plastic LQFP package, 14 mm x 20 mm
Sleep Mode : ZZ (Enables sleep mode, active high)
Ordering Information
Part number
Access time
Clock frequency
Package
μ
PD4443362GF-A75
3.8 ns
133 MHz
100-PIN PLASTIC LQFP (14 x 20)
#
#
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