- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄225472 > UPD44325084F5-E50-EQ2-A 4M X 8 QDR SRAM, 0.45 ns, PBGA165 PDF資料下載
參數(shù)資料
| 型號： | UPD44325084F5-E50-EQ2-A |
| 元件分類： | SRAM |
| 英文描述： | 4M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 39/40頁 |
| 文件大?。?/td> | 387K |
| 代理商： | UPD44325084F5-E50-EQ2-A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁
8
Data Sheet
M16784EJ4V0DS
μPD44325084, 44325094, 44325184, 44325364
Pin Identification
(1/2)
Symbol
Description
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. All transactions operate on a burst of four words (two clock periods of bus activity). These
inputs are ignored when device is deselected, i.e., NOP (R# = W# = HIGH).
D0 to Dxx
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K#
during WRITE operations. See Pin Configurations for ball site location of individual signals.
x8 device uses D0 to D7.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Q0 to Qxx
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges
if C and C# are tied HIGH. Data is output in synchronization with C and C# (or K and K#), depending on the R#
command. See Pin Configurations for ball site location of individual signals.
x8 device uses Q0 to Q7.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
R#
Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be
initiated. This input must meet setup and hold times around the rising edge of K. If a READ command (R# =
LOW) is input, an input of R# on the subsequent rising edge of K is ignored.
W#
Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be
initiated. This input must meet setup and hold times around the rising edge of K. If a WRITE command (W# =
LOW) is input, an input of W# on the subsequent rising edge of K is ignored.
BWx#
NWx#
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin
Configurations for signal to data relationships.
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
K, K#
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock rising edges.
C, C#
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
C# is used as the output timing reference for first and third output data. The rising edge of C is used as the
output reference for second and fourth output data. Ideally, C# is 180 degrees out of phase with C. When use of
K and K# as the reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed
unless C and C# are fixed to HIGH (i.e. toggle of C and C#).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPFS120P | P-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| UPL40-U1BT | CABLE TERMINATED, MALE, TNC CONNECTOR, PLUG |
| UPN2AS | FEMALE-FEMALE-MALE, RF Y ADAPTER |
| UPRLED630 | SINGLE COLOR LED, BRIGHT RED, 1.4732 mm |
| UPVLED | SINGLE COLOR LED, ULTRA VIOLET, 1.47 mm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44325092BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 4M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44325094BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325094BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325182BF5-E33-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD44325182BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。