參數(shù)資料
型號： UPD44325084F5-E50-EQ2-A
元件分類： SRAM
英文描述： 4M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁數(shù)： 11/40頁
文件大小： 387K
代理商： UPD44325084F5-E50-EQ2-A
19
Data Sheet
M16784EJ4V0DS
μPD44325084, 44325094, 44325184, 44325364
DC Characteristics (VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit Note
x8, x9 x18
x36
Input leakage current
ILI
–2
–
+2
μA
I/O leakage current
ILO
–2
–
+2
μA
Operating supply
IDD
Note1
Commercial
-E37
740 1,020 1,140 mA
current
(TA = 0 to +70°C)
-E40
700
950 1,050
(Read cycle /
-E50
600
800
900
Write cycle)
Industrial
-E40Y
800 1,090
–
(TA = –40 to +85°C) -E50Y
690
920
–
Standby supply
ISB1
Note1
Commercial
-E37
420
mA
current
(TA = 0 to +70°C)
-E40
400
(NOP)
-E50
350
Industrial
-E40Y
450
–
(TA = –40 to +85°C) -E50Y
400
–
Output HIGH voltage
VOH(Low) |IOH|
≤ 0.1 mA
VDDQ – 0.2
–
VDDQ
V
4, 5
VOH
Note2
VDDQ/2–0.12
–
VDDQ/2+0.12
V
4, 5
Output LOW voltage
VOL(Low) IOL
≤ 0.1 mA
VSS
–
0.2
V
4, 5
VOL
Note3
VDDQ/2–0.12
–
VDDQ/2+0.12
V
4, 5
Notes 1. VIN
≤ VIL or VIN ≥ VIH, II/O = 0 mA, Cycle = MAX.
2. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175
Ω ≤ RQ ≤ 350 Ω.
3. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175
Ω ≤ RQ ≤ 350 Ω.
4. AC load current is higher than the shown DC values.
5. HSTL outputs meet JEDEC HSTL Class I standards.
Capacitance (TA = 25
°C, f = 1 MHz)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Input capacitance (Address, Control)
CIN
VIN = 0 V
4
5
pF
Input / Output capacitance
CI/O
VI/O = 0 V
6
7
pF
(D, Q, CQ, CQ#)
Clock Input capacitance
Cclk
Vclk = 0 V
5
6
pF
Remark These parameters are periodically sampled and not 100% tested.
Thermal Resistance
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Thermal resistance
θ j-a
22.6
°C/W
(junction – ambient)
Thermal resistance
θ j-c
2.0
°C/W
(junction – case)
Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.
<R>
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