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參數(shù)資料
| 型號： | UPD178023 |
| 廠商： | NEC Corp. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 中文描述： | 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存 |
| 文件頁數(shù)： | 39/56頁 |
| 文件大?。?/td> | 261K |
| 代理商： | UPD178023 |
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39
μ
PD178023, 178024
Data Sheet U14126EJ1V0DS00
(2) Serial interface (T
A
= –40 to +85
°
C, V
DD
= 3.5 to 5.5 V)
(a) Serial interface (IIC0)
I
2
C bus mode
Parameter
Symbol
Standard Mode
High-speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
f
CLK
0
100
0
400
kHz
Bus free time (between stop and start
conditions)
t
BUF
4.7
–
1.3
–
μ
s
Hold time
Note 1
t
HD : STA
4.0
–
0.6
–
μ
s
SCL0 clock low-level width
t
LOW
4.7
–
1.3
–
μ
s
SCL0 clock high-level width
t
HIGH
4.0
–
0.6
–
μ
s
Start/restart condition setup time
t
SU : STA
4.7
–
0.6
–
μ
s
Data hold
CBUS compatible master
t
HD : DAT
5.0
–
–
–
μ
s
time
I
2
C bus
0
Note 2
–
0
Note 2
0.9
Note 3
μ
s
Data setup time
t
SU : DAT
250
–
100
Note 4
–
ns
SDA0 and SCL0 signal rise time
t
R
–
1000
20+0.1Cb
Note 5
300
ns
SDA0 and SCL0 signal fall time
t
F
–
300
20+0.1Cb
Note 5
300
ns
Stop condition setup time
t
SU : STO
4.0
–
0.6
–
μ
s
Pulse width of spike restrained by input filter
t
SP
–
–
0
50
ns
Each bus line capacitative load
Cb
–
400
–
400
pF
Notes 1.
The first clock pulse is generated at the start condition after this period.
2.
The device needs to internally supply a hold time of at least 300 ns for the SDA0 signal to fill the
undefined area at the falling edge of the SCL0 (V
IHmin.
of the SCL0 signal).
3.
Unless the device extends the low hold time (t
LOW
) of the SCL0 signal, it is necessary to fill only the
maximum data hold time (t
HD : DAT
).
4.
The high-speed mode I
2
C bus can be used in the standard mode I
2
C bus system. In this case, satisfy
the following conditions:
When the device does not extend the low hold time of the SCL0 signal
t
SU : DAT
≥
250 ns
When the device extends the low hold time of the SCL0 signal
Send the next data bit to the SDA line before releasing the SCL0 line (t
Rmax.
+ t
SU:DAT
= 1000 + 250
= 1250 ns : in the standard mode I
2
C bus specification)
5.
Cb: Total capacitance of one bus line (unit: pF)
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