參數(shù)資料
型號: UPA1790
廠商: NEC Corp.
英文描述: SWITCHING N-AND P-CHANNEL POWER MOS FET INDUSTRIAL USE
中文描述: 開關(guān)N溝道和P溝道功率場效應(yīng)晶體管工業(yè)用
文件頁數(shù): 4/8頁
文件大小: 53K
代理商: UPA1790
Data Sheet G14320EJ1V0DS00
4
μ
PA1790
P-CHANNEL
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Drain to Source On-state Resistance
R
DS(on)1
V
GS
= –10 V, I
D
= –0.35 A
0.45
0.6
R
DS(on)2
V
GS
= –4 V, I
D
= –0.35 A
0.74
1.1
Gate to Source Cut-off Voltage
V
GS(off)
V
DS
= –10 V, I
D
= –1 mA
–1.0
–1.7
–2.5
V
Forward Transfer Admittance
| y
fs
|
V
DS
= –10 V, I
D
= –0.35 A
5.0
S
Drain Leakage Current
I
DSS
V
DS
= –60 V, V
GS
= 0 V
–10
μ
A
Gate to Source Leakage Current
I
GSS
V
GS
=
#
16 V, V
DS
= 0 V
#
10
μ
A
Input Capacitance
C
iss
V
DS
= –10 V
230
pF
Output Capacitance
C
oss
V
GS
= 0 V
100
pF
Reverse Transfer Capacitance
C
rss
f = 1 MHz
25
pF
Turn-on Delay Time
t
d(on)
I
D
= –0.35 A
1.9
ns
Rise Time
t
r
V
GS(on)
= –10 V
1.7
ns
Turn-off Delay Time
t
d(off)
V
DD
= –30 V
30
ns
Fall Time
t
f
R
G
= 10
15
ns
Total Gate Charge
Q
G
I
D
= –0.7 A
7.6
nC
Gate to Source Charge
Q
GS
V
DD
= –48 V
1
nC
Gate to Drain Charge
Q
GD
V
GS
= –10 V
2
nC
Body Diode Forward Voltage
V
F(S-D)
I
F
= 0.7 A, V
GS
= 0 V
0.85
V
Reverse Recovery Time
t
rr
I
F
= 0.7 A, V
GS
= 0 V
58
ns
Reverse Recovery Charge
Q
rr
di/dt = 100 A
/
μ
s
130
nC
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
PG.
R
0
V
GS
D.U.T.
R
L
V
DD
τ
= 1 s
Duty Cycle
1 %
V
GS
Wave Form
D
Wave Form
V
GS
10 %
90 %
V
GS(on)
10 %
0
I
D
90 %
90 %
t
d(on)
t
r
t
d(off)
t
f
10 %
τ
R
G
= 10
I
D
0
t
on
t
off
PG.
50
D.U.T.
R
L
V
DD
I
G
= 2 mA
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