參數(shù)資料
型號： UM_S3C49F9X
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： S3C49F9X User’s Manual
中文描述： S3C49F9X用戶手冊
文件頁數(shù)： 18/74頁
文件大?。?/td> 653K
代理商： UM_S3C49F9X
S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION
18
Table 2-5 Pin description for external memory interface(Cont.)
Signal
Name
100-Pin
Number
I/O
Description
TCK
87
I
TEST CLOCK : The KS32P49F9X contains internally in-circuit emulation block
for debugger mode which use standard JTAG protocol. When the controller go
into debugger mode, this signal is provided from external debugger tool.
TMS
86
I
TEST MODE SELECT : In the debugger mode, this signal select test mode.
This pin should be held to “1’, when do not use the JTAG block.
TDI
85
I
TEST DATA INPUT : In the debugger mode, this signal is used for carry data.
from external debugger tool to the controller.
nTRST
81
I
TEST RESET : This signal should be sustained LOW first at the begging of
normal operation.
TDO
80
I/O
TEST DATA OUTPUT : In the debugger mode, this signal is used for carry
data. from the controller to external debugger tool.
XI
62
OC
INPUT CLOCK : This signal is system clock.
XO
63
OC
OUTPUT CLOCK :
nRESET
-
I
RESET : This pin is system power on reset . A low input will stop all operation
within the controller.
SW1
-
I
ROM SELECTION : This pin is used for select ROM. When this signal set “1”,
the controller access external ROM. When this pin is “0”, the controller access
internal ROM.
SW0
-
I
FLASH NUMBER OF SELECTION : Basically flash memory can be connected
up to 20. But if use the external buffer on pc card , flash memory can be
connected up to 32. This signal is used for select number of flash. When this
signal is high, can be connected up to 20. In the case of low, can be connected
up to 32.
CTEST
74
I
CORE TEST : This signal is used for test CPU(ARM7TDMI) core. When this
signal is low(0), the controller operate normal mode. When it is high(1), operate
CPU test mode.
CMODE
-
I
INTERRUPT ENABLE : This signal is used for control interrupt signal of CPU,
when the signal is set(1), interrupt signal of CPU can be enabled. When this
signal is cleared(0), interrupt signal can be disabled.
TEST1
TEST2
82
83
I
I
OTP MODE SELECT : These signals are used for select OTP mode. When
OTPMS1 and OTPMS2 are low, the controller operate normal mode. To
operate the OTP mode, OTPMS1 and OTPMS2 signal should be set to low and
high. The others setting mode are reserved for chip maker.
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