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參數(shù)資料
| 型號(hào)： | UM_S3C49F9X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | S3C49F9X User’s Manual |
| 中文描述： | S3C49F9X用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 10/74頁(yè) |
| 文件大小： | 653K |
| 代理商： | UM_S3C49F9X |
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S3C49F9X SOLID DISK CONTROLLER PIN INFORMATION
10
2.3 Pin description for host interface
Table 2-3 Pin description for host interface
Signal
Name
100-Pin
Number
I/O
Description
XARD0
XARD1
XARD2
XARD3
XARD4
XARD5
XARD6
XARD7
XARD8
XARD9
XARD10
5
6
7
8
9
11
12
13
17
18
22
I
ADDRESS BUS[10:0] : These address lines along with the –REG signal are used
to select the following: The I/O port address registers within the PC Storage Card,
the memory mapped port address registers within the PC Storage Card, a byte in
the Card's information structure and its configuration control and status registers.
This signal is the same as the PC Card Memory Mode signal in PC Card I/O
mode.
In True IDE Mode only A[2:0] are used to select the one of eight registers in the
Task File, the remaining address lines should be grounded by the host.
XDB0
XDB1
XDB2
XDB3
XDB4
XDB5
XDB6
XDB7
XDB8
XDB9
XDB10
XDB11
XDB12
XDB13
XDB14
XDB15
94
93
92
37
36
35
34
33
91
90
89
31
30
29
28
27
I/O
DATA BUS[15:0] : These lines carry the Data, Commands and Status information
between the host and the controller. XDB0 is the LSB of the even byte of the word.
XDB8 is the LSB of the odd byte of the word.
This signal is the same as the PC Card memory mode signal in PC Card I/O
mode.
In True IDE mode, all Task File operations occur in byte mode on the low order
bus XDB0-XDB7 while all data transfers are 16 bit using XDB0-XDB15.
XREG
99
I
ATTRIBUTE MEMORY AREA SELECTION : This signal is used during memory
cycles to distinguish between common memory and register (Attribute) memory
accesses. High for Common memory, low for attribute memory.
The signal must also be active (low) during I/O cycles when the I/O address is on
the Bus.
In True IDE mode, this input signal is not used and should be connected to VCC
by the host.
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