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參數(shù)資料
| 型號： | UCC2919DTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | GREEN, PLASTIC, MS-012AC, SOIC-16 |
| 文件頁數(shù)： | 25/27頁 |
| 文件大小： | 701K |
| 代理商： | UCC2919DTR |
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UCC2919
UCC3919
SLUS374C JULY 1999 REVISED NOVEMBER 2005
7
www.ti.com
APPLICATION INFORMATION
The UCC3919 monitors the voltage drop across a high side sense resistor and compares it against three
different voltage thresholds. These are discussed below. Figure 1 shows the UCC3919 waveforms under fault
conditions.
fault threshold
The first threshold is fixed at 50 mV. If the current is high enough such that the voltage on CSN is 50 mV below
CSP, the timing capacitor CT begins to charge at about 35 A if the PL pin is open. (Power limiting will be
discussed later). If this threshold is exceeded long enough for CT to charge to 1.5 V, a fault is declared and the
external MOSFET will be turned off. It will either be latched off (until the power to the circuit is cycled, the L/R
pin is taken low, or the SD pin is toggled), or will retry after a fixed off time (when CT has discharged to 0.5 V),
depending on whether the L/R pin is set high or low by the user. The equation for this current threshold is simply:
I
FAULT +
0.05
R
SENSE
The first time a fault occurs, CT is at ground, and must charge to 1.5 V. Therefore:
t
FAULT +
t
ON(sec) +
Ct(mF)
1.5
35
In the retry mode, the timing capacitor will already be charged to 0.5 V at the end of the off time, so all subsequent
cycles will have a shorter ton time, given by:
t
FAULT ^
t
ON(sec) +
C
T
(
mF)
35
Note that these equations for tON are without the power limiting feature (RPL pin open). The effects of power
limiting on tON will be discussed later.
The off time in the retry mode is set by CT and an internal 1.2-A sink current. It is the time it takes CT to discharge
from 1.5 V to 0.5 V. The equation for the off time is therefore:
t
OFF(sec) +
C
Tm
F
1.2
shutdown characteristics
When the SD pin is set to TTL high (above 2 V) the UCC3919 is ensured to be enabled. When SD is set to a
low TTL (below 0.8 V) the UCC3919 is ensured to be disabled, but may not be in ultra low current sleep mode.
When SD is set to 0.2 V or less, the UCC3919 is ensured to be disabled and in ultra low current sleep mode.
See Figure 1. At cold temperatures, (below 0
°C), the UCC2919 shutdown supply current delays gradually over
time and may take >1 minute to drop below the 7-
A shutdown current limit. However, the gate output is driven
low immediately when the SD pin is pulled low and does not exhibit a temperature dependency.
(1)
(2)
(3)
(4)
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