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參數(shù)資料
| 型號(hào)： | UCC2919DTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | GREEN, PLASTIC, MS-012AC, SOIC-16 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大小： | 701K |
| 代理商： | UCC2919DTR |
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UCC2919
UCC3919
SLUS374C JULY 1999 REVISED NOVEMBER 2005
6
www.ti.com
pin descriptions (continued)
GATE
The output of the linear current amplifier. This pin drives the gate of an external N-channel MOSFET pass
transistor. The linear current amplifier control loop is internally compensated, and ensured stable for output load
(gate) capacitance between 100 pF and 0.01
F. In applications where the GATE voltage (or charge pump
voltage) exceeds the maximum gate-to-source voltage ratings (VGS) for the external N-channel MOSFET, a
Zener clamp may be added to the gate of the MOSFET. No additional series resistance is required since the
internal charge pump has a finite output impedance of 100-k
typical.
GND
The ground reference for the device.
IBIAS
Output of the on board bias generator internally regulated to 1.5 V below CSP. A resistor divider between this
pin and CSP can be used to generate the IMAX voltage. The bias circuit is internally compensated, and requires
no bypass capacitance. If an external bypass is required due to a noisy environment, the circuit will be stable
with up to 0.001
F of capacitance. The bypass must be to CSP, since the bias voltage is generated with respect
to CSP. Resistor R2 (Figure 5) should be greater than 50 k
to minimize the effect of the finite input impedance
of the IBIAS pin on the IMAX threshold.
IMAX
Used to program the maximum allowable sourcing current. The voltage on this pin is with respect to CSP. If the
voltage across the shunt resistor exceeds this voltage the linear current amplifier lowers the voltage at GATE
to limit the output current to this level. If the voltage across the shunt resistor goes more than 200 mV beyond
this voltage, the gate drive pin GATE is immediately driven low and kept low for one full off time interval.
L/R
Latch/Reset. This pin sets the reset mode. If L/R is low and a fault occurs the device will begin duty ratio current
limiting. If L/R is high and a fault occurs, GATE will go low and stay low until L/R is set low. This pin is internally
pulled low by a 3-
A nominal pulldown.
PL
Power Limit. This pin is used to control average power dissipation in the external MOSFET. If a resistor is
connected from this pin to the source of the external MOSFET, the current in the resistor will be roughly
proportional to the voltage across the FET. As the voltage across the FET increases, this current is added to
the fault timer charge current, reducing the on time duty cycle from its nominal value of 3% and limiting the
average power dissipation in the FET.
SD
Shutdown pin. If this pin is taken low, GATE will go low, and the IC will go into a low current standby mode and
CT will be discharged. This TTL compatible input must be driven high to turn on.
VDD
The power connection for the device.
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