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參數(shù)資料
| 型號： | UAA3580 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Wideband code division multiple access frequency division duplex zero IF receiver |
| 中文描述： | 寬帶碼分多址頻分雙工零中頻接收機 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 107K |
| 代理商： | UAA3580 |
2002 Oct 30
18
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
15 SERIAL BUS TIMING CHARACTERISTICS
V
CCA
= 2.6 V; V
CCA(CP)
= 2.6 V; V
DDD
= 1.6 V; T
amb
= 25
°
C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial clock; pin CLK
t
i(r)
t
i(f)
T
cyc
Enable; pin EN
input rise time
input fall time
clock period
67
20
20
ns
ns
ns
t
d(START)
t
d(END)
t
W
t
su;EN
Register serial input data; pin DATA
delay to rising clock edge
delay from last falling clock edge
minimum inactive pulse width
enable set-up time to next clock
200
100
400
200
ns
ns
ns
ns
t
su;DATA
t
h;DATA
input data to clock set-up time
input data to clock hold time
25
25
ns
ns
handbook, full pagewidth
MGU575
tsu;DAT
td(START)
tW
th;DAT
ti(f)
ti(r)
td(END)
tsu;EN
Tcyc
CLK
DATA
MSB
LSB
ADDRESS
EN
Fig.3 Serial bus timing diagram.
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