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參數(shù)資料
| 型號： | UAA3580 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Wideband code division multiple access frequency division duplex zero IF receiver |
| 中文描述： | 寬帶碼分多址頻分雙工零中頻接收機 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 107K |
| 代理商： | UAA3580 |
2002 Oct 30
15
Philips Semiconductors
Objective specification
Wideband code division multiple access
frequency division duplex zero IF receiver
UAA3580
14 AC CHARACTERISTICS
V
CCA
= 2.6 V; T
amb
= 25
°
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RF receiver inputs; pins RFIN and RFIP
f
i(RF)
R
i
C
i
s
11
F
RF input frequency
input resistance
input capacitance
input power matching
noise figure
2.11
170
1
10
3.2
2.17
4
GHz
pF
dB
dB
with external balun
in receive mode with
maximum gain
in receive mode with
maximum gain
in receive mode with
maximum gain;
interference 20 MHz
away from channel
bandwidth
in receive mode with
maximum gain;
interferers 190 MHz away
from channel bandwidth
at 15 MHz offset
CP
1
1 dB compression point
23
20
dBm
IP
3
input referred 3rd-order
intercept point
18
15
dBm
IP
2
input referred 2nd-order
intercept point
37
42
dBm
n
Baseband IQ section; pins IP, IN, QP and QN
phase noise
135
dBc/Hz
G
v(max)
G
v(min)
AGC
tot
G
step(AGC)
AGC
tot(lin)
G
v(IQ)
maximum voltage gain
minimum voltage gain
total AGC range
AGC gain step
total AGC linearity
voltage gain mismatch
between the I and Q paths
quadrature phase error
between the I and Q paths
maximum output voltage per
pin
maximum output current per
pin
92
12
0.5
96
17
79
1
100
22
+0.5
0.5
dB
dB
dB
dB
dB
dB
Φ
peak error
5
deg
V
o(max)
R
L(diff)
= 10 k
;
THD < 3%
V
o(p-p)
= 1.75 V at 1 MHz;
R
L(diff)
= 10 k
;
C
L(diff)
= 20 pF
0.75
V
I
o(max)
650
μ
A
V
offset(diff)
differential output offset
voltage
3 dB high-pass corner
frequency
3 dB low-pass corner
frequency
group delay variation
20
+20
mV
HP
3dB
2nd-order high-pass
frequency
5th-order low-pass
frequency
100 kHz < f
o
< 2 MHz
10
15
20
kHz
LP
3dB
2.25
2.4
2.55
MHz
d
(g)
260
ns
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