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參數(shù)資料
| 型號： | UAA3515A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 900 MHz analog cordless telephone IC |
| 中文描述： | 900 MHz模擬無繩電話芯片 |
| 文件頁數(shù)： | 17/44頁 |
| 文件大?。?/td> | 180K |
| 代理商： | UAA3515A |
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2001 Dec 12
17
Philips Semiconductors
Product specification
900 MHz analog cordless telephone IC
UAA3515A
7.7
Voltage regulator
Pin V
REG
provides the internal supply voltage for the
RX and TX PLLs. It is regulated at 2.7 V nominal voltage.
Two capacitors of 4.7
μ
F and 100 nF must be connected
topinV
REG
tofilterandstabilizethisregulatedvoltage.The
tolerance of the regulated voltage is initially
±
8% but is
improved to
±
2% after the internal bandgap voltage
reference is adjusted through the microcontroller.
7.8
Low-battery detection
The low-battery detector measures the voltage level of the
V
CC
using a resistance divider and a comparator. One
inputofthecomparatorisconnectedto VB,theothertothe
middle point of the resistance divider. The comparator has
a built-in hysteresis to prevent spurious switching. The
precision of the detection depends on the divider
accuracy, the comparator offset and the accuracy of the
reference voltage VB. The output is multiplexed at pin
CDLBD. When the battery voltage level is under the
threshold voltage the output CDLBD is going LOW.
7.9
Microcontroller interface
The DATA, CLK and EN pins provide a 3-wire
unidirectional serial interface for programming the
reference counters, the transmit and receive channel
divider-counters and the control functions.
The interface consists of 19-bit shift registers connected to
a matrix of registers organized as 7 words of 16 bits (all
are control registers). The leading 16 bits include the data
D15 to D0. The trailing 3 bits set up the address AD2 to
AD0. The data is entered with the most significant bit D15
first and the last bit is AD0.
Pins DATA and CLK are used to load data into the shift
register. Figure 10 shows the timing required on all pins.
Data is clocked into the shift registers on negative clock
transitions.
A new clock divider ratio is enabled using an extra EN
rising edge. Minimum hold time is 50 ns and during this
time no clock cycle is allowed. These extra EN edges can
be applied to all the data programmed but will have no
effect on the serial interface programming.
The pins DATA, CLK and EN are supplied by V
REG
. The
ESD protection diodes on these pins are connected to
V
CC
.
相關PDF資料 |
PDF描述 |
|---|---|
| UAA3515AHL | 900 MHz analog cordless telephone IC |
| UAA3522 | Low power dual-band GSM transceiver with an image rejecting front-end |
| UAA3522HL | Low power dual-band GSM transceiver with an image rejecting front-end |
| UAA3535 | Low power GSM/DCS/PCS multi-band transceiver |
| UAA3535HL | Low power GSM/DCS/PCS multi-band transceiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UAA3515AHL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:900 MHz analog cordless telephone IC |
| UAA3522 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low power dual-band GSM transceiver with an image rejecting front-end |
| UAA3522HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low power dual-band GSM transceiver with an image rejecting front-end |
| UAA3535 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low power GSM/DCS/PCS multi-band transceiver |
| UAA3535HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low power GSM/DCS/PCS multi-band transceiver |
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