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參數(shù)資料
| 型號(hào)： | UAA3202 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Frequency Shift Keying FSK receiver |
| 中文描述： | 頻移鍵控FSK接收器 |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | UAA3202 |
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1997 Aug 12
8
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
AC CHARACTERISTICS
V
CC
= 3.5 V; T
amb
= 25
°
C; for application diagram see Fig.11; f
i
= 433.92 MHz;
f =
±
25 kHz; f
mod
= 250 Hz square
wave, i.e. 500 bits/s; unless otherwise specified.
Notes
1.
2.
Measured at the RF input connector of the test board.
Measured at test point A in Fig.11.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System performance
P
sens
P
i(max)
α
rad
t
st
B
IF
f
D
Mixer
G
mix
R
o(mix)
Post mixer amplifier
IP3
PMA
G
PMA
P
<1dB
BW
PMA
R
oPMA
Limiter
G
lim
B
lim
R
i(lim)
Demodulator
G
DMOD
sensitivity
maximum input power
spurious radiation
receiver settling time
IF bandwidth range
data frequency
BER
≤
3%
BER
≤
3%
note 1
P
i
= P
sens
+ 10 dB; see Fig.5
P
i
= P
sens
+ 3 dB
850
140
2
1000
94
30
60
5
1150
250
dBm
dBm
dBm
ms
kHz
Hz
mixer conversion gain
mixer output resistance
31
2.7
33
3
35
3.3
dB
k
interception point (mixer + PMA)
PMA gain
compression (mixer + PMA)
PMA LP cut-off frequency
PMA output resistance
note 2
note 2
P
i
=
45 dBm
38
9
0
5
1.2
35
10.4
1.4
12
1
1.6
dBm
dB
dBm
MHz
k
limiter gain
limiter LP cut-off frequency
limiter input resistance
60
2
40
63.5
5
50
67
8
60
dB
MHz
k
demodulator gain
note 2
0.8
1
1.2
f
c(DMOD)
f
R
o(DMOD)
Data slicer
B
DS
R
o(DS)
RSSI comparator
V
o(RSSI)
V
o(COMP)
P
th(on)
demodulator centre frequency
frequency deviation
demodulator output resistance
800
20
24
1000
25
30
1200
70
36
kHz
kHz
k
data slicer bandwidth
data slicer output resistance
35
120
50
150
180
kHz
k
RSSI output voltage
COMP output voltage
threshold for switching COMP output
voltage to HIGH
hysteresis width of COMP output voltage
see Fig.3
see Fig.4
99.5
95.5
91.5
dBm
P
hys(W)
1
2
4
dBm
kHz
mV
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相關(guān)代理商/技術(shù)參數(shù) |
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