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參數(shù)資料
| 型號： | U631H64S2C45 |
| 元件分類： | SRAM |
| 英文描述： | 8K X 8 NON-VOLATILE SRAM, 45 ns, PDSO28 |
| 封裝： | 0.330 INCH, SOP2-28 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 131K |
| 代理商： | U631H64S2C45 |
U631H64
8
March 31, 2006
STK Control #ML0045
Rev 1.0
n:
The software sequence is clocked with E controlled READs.
Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p:
Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q:
An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
r:
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s:
If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
No. Software Controlled STORE/RECALL
Cyclel, n
Symbol
25
35
45
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
25 STORE/RECALL Initiation Time
tAVAV
tcR
25
35
45
ns
26 Chip Enable to Output Inactiveo
tELQZ
tdis(E)SR
600
ns
27 STORE Cycle Timep
tELQXS
td(E)S
10
ms
28 RECALL Cycle Timeq
tELQXR
td(E)R
20
μs
29 Address Setup to Chip Enabler
tAVELN
tsu(A)SR
00
0
ns
30 Chip Enable Pulse Widthr, s
tELEHN
tw(E)SR
20
25
35
ns
31 Chip Disable to Address Changer
tEHAXN
th(A)SR
00
0
ns
Ai
E
DQi
Output
tcR
tw(E)SR
High Impedance
ADDRESS 1
VALID
Software Controlled STORE/RECALL Cycler, s, t, u (E = HIGH after STORE initiation)
ADDRESS 6
tcR
(25)
th(A)SR
(31)
(30)
tsu(A)SR
Ai
E
DQi
Output
tcR
tw(E)SR
High Impedance
ADDRESS 1
VALID
ADDRESS 6
td(E)S (27)
(28)
(25)
th(A)SR
(31)
(30)
tsu(A)SR (29)
tdis(E)SR (26)
th(A)SR (31)
tsu(A)SR
(29)
tw(E)SR
th(A)SR
(31)
(30)
tsu(A)SR
(29)
(5)
tdis(E)
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
tdis(E)SR (26)
(29)
td(E)S (27)
(28)
td(E)R
t:
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U631H64 performs a STORE
or RECALL.
u:
E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| U631H64S2C45G1 | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:SoftStore 8K x 8 nvSRAM |
| U631H64S2K25 | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:SoftStore 8K x 8 nvSRAM |
| U631H64S2K25G1 | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:SoftStore 8K x 8 nvSRAM |
| U631H64S2K35 | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:SoftStore 8K x 8 nvSRAM |
| U631H64S2K35G1 | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:SoftStore 8K x 8 nvSRAM |
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