參數(shù)資料
型號: U631H64S2C45
元件分類: SRAM
英文描述: 8K X 8 NON-VOLATILE SRAM, 45 ns, PDSO28
封裝: 0.330 INCH, SOP2-28
文件頁數(shù): 11/13頁
文件大?。?/td> 131K
代理商: U631H64S2C45
U631H64
7
March 31, 2006
STK Control #ML0045
Rev 1.0
No.
STORE Cycle Inhibit and
Automatic Power Up RECALL
Symbol
Min.
Max.
Unit
Alt.
IEC
24 Power Up RECALL Durationk, e
tRESTORE
650
μs
Low Voltage Trigger Level
VSWITCH
4.0
4.5
V
Nonvolatile Memory Operations
STORE Cycle Inhibit and Automatic Up RECALL
k:
tRESTORE starts from the time VCC rises above VSWITCH.
VCC
5.0 V
STORE inhibit
Power Up
VSWITCH
tRESTORE
RECALL
(24)
t
Software Mode Selection
E
W
A12 - A0
(hex)
Mode
I/O
Power
Notes
L
H
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Nonvolatile STORE
Output Data
Output High Z
Active
ICC2
l, m
l
L
H
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Nonvolatile RECALL
Output Data
Output High Z
Active
l, m
l
l:
The six consecutive addresses must be in order listed (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a Store cycle or (0000, 1555, 0AAA,
1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and
diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C.
m: I/O state assumes that G
≤ V
IL. Activation of nonvolatile cycles does not depend on the state of G.
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