參數(shù)資料
型號: U631H64BSK45
元件分類: SRAM
英文描述: 8K X 8 NON-VOLATILE SRAM, 45 ns, PDSO28
封裝: 0.330 INCH, SOP1-28
文件頁數(shù): 1/13頁
文件大小: 131K
代理商: U631H64BSK45
U631H64
Obsolete - Not Recommended for New Designs
1
March 31, 2006
STK Control #ML0045
Rev 1.0
High-performance CMOS non-
volatile static RAM 8192 x 8 bits
25, 35 and 45 ns Access Times
12, 20 and 25 ns Output Enable
Access Times
Software STORE Initiation
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20
μs)
Unlimited RECALL cycles from
EEPROM
Unlimited Read and Write to
SRAM
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70
°C
-40 to 85
°C
QS 9000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
RoHS compliance and Pb- free
Packages: PDIP28 (300 mil)
SOP28 (330 mil)
Description
The U631H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H64 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM
to
the
SRAM
(the
RECALL
operation) are initiated
through software sequences.
The U631H64 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
SoftStore 8K x 8 nvSRAM
Pin Configuration
Pin Description
Top View
1
n.c.
VCC
28
2
A12
W
27
4
A6
A8
25
5
A5
A9
24
3
A7
n.c.
26
6
A4
A11
23
7
A3
G
22
8
A2
A10
21
12
DQ1
DQ5
17
9
A1
E
20
10
A0
DQ7
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
PDIP
SOP
Signal Name
Signal Description
A0 - A12
Address Inputs
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Power Supply Voltage
VSS
Ground
Features
相關(guān)PDF資料
PDF描述
U631H64S2C45 8K X 8 NON-VOLATILE SRAM, 45 ns, PDSO28
U84-W-9 GENERAL PURPOSE INDUCTOR
U84-W-6 GENERAL PURPOSE INDUCTOR
U84-W-68 GENERAL PURPOSE INDUCTOR
U84-W-64 GENERAL PURPOSE INDUCTOR
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