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參數(shù)資料
| 型號： | U62H64DK25L |
| 元件分類： | SRAM |
| 英文描述： | 8K X 8 STANDARD SRAM, 25 ns, PDIP28 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 119K |
| 代理商： | U62H64DK25L |
December 12, 1997
31
0
U62H64
Switching Characteristics
Symbol
Min.
Max.
Unit
Alt.
IEC
20
25
35
20
25
35
Time to Output in Low-Z from
E1 LOW or E2 HIGH
G LOW
W HIGH
t
LZCE
t
LZOE
t
LZWE
t
en(E)
t
en(G)
t
en(W)
5
0
0
5
0
0
5
0
0
ns
ns
ns
Cycle Time
Write Cycle Time
Read Cycle Time
t
WC
t
RC
t
cW
t
cR
20
20
25
25
35
35
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
t
ACE
t
OE
t
AA
t
a(E)
t
a(G)
t
a(A)
20
10
20
25
12
25
35
15
35
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
t
WP
t
CW
t
w(W)
t
w(E)
15
15
15
20
20
25
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
t
AS
t
CW
t
WP
t
DS
t
su(A)
t
su(E)
t
su(W)
t
su(D)
0
15
15
10
0
20
15
10
0
25
20
15
ns
ns
ns
ns
Data Hold Time
Address Hold from End of Write
t
DH
t
AH
t
h(D)
t
h(A)
0
0
0
0
0
0
ns
ns
Output Hold Time from Address Change
t
OH
t
v(A)
5
5
5
ns
E1 HIGH or E2 LOW to Output in
High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
HZCE
t
HZWE
t
HZOE
t
dis(E)
t
dis(W)
t
dis(G)
8
8
8
10
10
10
15
15
12
ns
ns
ns
E1 LOW or E2 HIGH to Power-Up
t
PU
0
0
0
ns
E1 HIGH or E2 LOW to Power-Down
t
PD
20
25
35
ns
V
CC(DR)
≥
2 V
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
4.5 V
V
CC
E1
V
CC(DR)
≥
2 V
V
E2(DR)
≥
V
CC(DR)
- 0.2 V or V
E2(DR)
≤
0.2 V
V
CC(DR)
- 0.2 V
≤
V
E1(DR)
≤
V
CC(DR)
+ 0.3 V
0 V
0.8 V
0.8 V
2.2 V
2.2 V
4.5 V
0 V
V
CC
E2
V
E1(DR)
≥
V
CC(DR)
- 0.2 V or V
E1(DR)
≤
0.2 V
V
E2(DR)
≤
0.2 V
t
DR
Data Retention
t
rec
t
rec
t
DR
Data Retention
Chip Deselect to Data Retention Time
Operating Recovery Time at V
CC(DR)
t
DR
:
t
rec
:
min 0 ns
min t
cR
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