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參數(shù)資料
| 型號： | U62H64DK25L |
| 元件分類： | SRAM |
| 英文描述： | 8K X 8 STANDARD SRAM, 25 ns, PDIP28 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 119K |
| 代理商： | U62H64DK25L |
December 12, 1997
3
08
U62H64
*H or L
Operating Mode
E1
E2
W
G
DQ0 - DQ7
Standby/not
selected
*
L
*
*
High-Z
H
*
*
*
High-Z
Internal Read
L
H
H
H
High-Z
Read
L
H
H
L
Data Outputs Low-Z
Write
L
H
L
*
Data Inputs High-Z
Truth Table
Block Diagram
A0
A1
A2
A3
A4
A5
Memory Cell
Array
128 Rows
64 x 8 Columns
B
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
* Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 s.
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
V
I
V
O
T
a
-0.3
7
V
Input Voltage
-0.3
V
CC
+ 0.5
V
CC
+ 0.5
70
85
85
V
Output Voltage
-0.3
V
Operating Temperature
C-Type
G-Type
K-Type
0
-25
-40
°
C
°
C
°
C
Storage Temperature
T
stg
|I
OS
|
-55
125
°
C
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
*
300
mA
E2
E1
Characteristics
V
CC
V
SS
W
G
R
I
R
Sense Amplifier/
Write Control Logic
Clock
Generator
C
I
C
Address
Change
Detector
A6
A7
A8
A9
A10
A11
A12
All voltages are referenced to V
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
3 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
= 0 V and V
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and ten-times, in which cases transition is measured
±
200 mV from steady-state voltage.
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| U62H64SA35 | 制造商:ZMD 制造商全稱:Zentrum Mikroelektronik Dresden AG 功能描述:AUTOMOTIVE FAST 8K X 8 SRAM |
| U62H64SA35G1 | 制造商:ZMD 制造商全稱:Zentrum Mikroelektronik Dresden AG 功能描述:AUTOMOTIVE FAST 8K X 8 SRAM |
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