
U430/431
Siliconix
P-37405—Rev. D, 04-Jul-94
1
Matched N-Channel JFET Pairs
Product Summary
Part Number
V
GS(off)
(V)
V
(BR)GSS
Min (V)
g
fs
Min (mS)
I
G
Typ (pA)
V
GS1
– V
GS2
Typ (mV)
U430
–1 to –4
–25
10
–15
25
U431
–2 to –6
–25
10
–15
25
Features
Two-Chip Design
High Slew Rate
Low Offset/Drift Voltage
Low Gate Leakage: 15 pA
Low Noise
High CMRR: 75 dB
Benefits
Tight Differential Match vs. Current
Improved Op Amp Speed, Settling Time Accuracy
Minimum Input Error/Trimming Requirement
Insignificant Signal Loss/Error Voltage
High System Sensitivity
Minimum Error with Large Input Signals
Applications
Wideband Differential Amps
High-Speed,
Temp-Compensated,
Single-Ended Input Amps
High-Speed Comparators
Impedance Converters
Description
The U430/431 are matched JFET pairs assembled in a
TO-78 package. These devices offer good power gain
even at frequencies beyond 250 MHz.
The TO-78 package is available with full military
processing (see Military Information).
For similar products, see the low-noise U/SST401 series,
the high-gain 2N5911/5912, and the low-leakage
U421/423 data sheets.
1
TO-78
Top View
D
1
S
1
2
3
7
6
5
G
1
S
2
G
2
D
2
4
Case
Absolute Maximum Ratings
Gate-Drain, Gate-Source Voltage
Gate Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (
1
/
16
” from case for 10 sec.)
Storage Temperature
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature
–25 V
10 mA
300 C
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . .
–65 to 200 C
–55 to 150 C
. . . . . . . . . . . . . . . . . .
Power Dissipation :
Per Side
a
Total
b
300 mW
500 mW
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
Notes
a.
b.
Derate 2.4 mW/ C above 25 C
Derate 4 mW/ C above 25 C
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70249.