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參數(shù)資料
| 型號(hào)： | U2402B-X |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDIP18 |
| 封裝： | DIP-18 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 294K |
| 代理商： | U2402B-X |
U2402B
Rev. A4, 08-Nov-99
8 (18)
Analog-Digital-Converter (ADC),
Test Sequence
A special analog-digital-converter consists of a five-bit
coarse and a five-bit fine converter . It operates by a linear
count method which can digitalize a battery voltage of
4 V at Pin 10 in 6.5 mV steps of sensitivity.
In a duty cycle, T, of 20.48 s, the converter executes the
measurement from a standard oscillation frequency of
fosc = 800 Hz. The voltage measurement is during the
charge break time of 2.56 s (see figure 8), i.e., no-load
voltage (or currentless phase). Therefore it has optimum
measurement accuracy because all interferences are
cut-off during this period (e.g., terminal resistances or
dynamic load current fluctuations).
After a delay of 1.28 s the actual measurement phase of
1.28 s follows. During this idle interval of cut-off
conditions, battery voltage is stabilized and hence
measurement is possible.
An output pulse of 10 ms appears at Pin 9 during charge
break after a delay of 40 ms. The output signal can be used
in a variety of way, e.g., synchronising the test control
(reference measurement).
Plausibility for Charge Break
There are two criterian considered for charge break
plausibility:
–
DV Cut-Off
When the signal at Pin 10 of the DA converter is 12 mV
below the actual value, the comparator identifies it as a
voltage drop of – dV. The validity of – dV cutt-off is
considered only if the actual value is below 12 mV for
three consective cycles of measurement.
d2V/dt2 Cut-Off
A four bit forward/ backward counter is used to register
the slope change (d2V/dt2, VBatt – slope). This counter is
clocked by each tracking phase of the fine AD-counter.
Beginning from its initial value, the counter counts the
first eight cycles in forward direction and the next eight
cycles in reverse direction. At the end of 16 cycles, the
actual value is compared with the initial value. If there is
a difference of more than two LSB-bit (13.5 mV) from the
actual counter value, then there is an identification of
slope change which leads to normal charge cut-off. A
second counter in the same configuration is operating in
parallel with eight clock cycles delay, to reduce the total
cut-off delay, from 16 test cycles to eight test cycles.
2.56 s
T= 20.48 s
t
10 ms
40 ms
t
1.28 s
charge
break
output
Status
ADC
conversion
time
(internal)
Charge
Charge break
Figure 8. Operating sequence of voltage measurements
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