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鍨嬭櫉(h脿o)锛� U1AFS600-FGG256
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 144/334闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA FUSION SIL SCULP 256FBGA
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绯诲垪锛� Fusion®
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 114
闁€(m茅n)鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
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Device Architecture
2-212
Revision 4
Differential I/O Characteristics
Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer
software when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires
that one data bit be carried through two signal lines, so two pins are needed. It also requires external
resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-134.
The building blocks of the LVDS transmitter鈥搑eceiver are one transmitter macro, one receiver macro,
three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three
driver resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Figure 2-134 LVDS Circuit Diagram and Board-Level Implementation
Table 2-168 Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min.
Typ.
Max.
Units
VCCI
Supply Voltage
2.375
2.5
2.625
V
VOL
Output Low Voltage
0.9
1.075
1.25
V
VOH
Input High Voltage
1.25
1.425
1.6
V
IOL 1
Output Low Voltage
0.65
0.91
1.16
mA
IOH 1
Output High Voltage
0.65
0.91
1.16
mA
VI
Input Voltage
0
2.925
V
IIL 2,3
Input Low Voltage
10
A
IIH 2,4
Input High Voltage
10
A
VODIFF
Differential Output Voltage
250
350
450
mV
VOCM
Output Common Mode Voltage
1.125
1.25
1.375
V
VICM
Input Common Mode Voltage
0.05
1.25
2.35
V
VIDIFF
Input Differential Voltage
100
350
mV
Notes:
1. IOL/IOH defined by VODIFF/(Resistor Network)
2. Currents are measured at 85掳C junction temperature.
3. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
140
100
ZO = 50
ZO = 50
165
165
+
鈥�
P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA
Bourns Part Number: CAT16-LV4F12
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