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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� U1AFS600-FG256
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 191/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA FUSION SIL SCULP 256FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� Fusion®
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 114
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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DC and Power Characteristics
3-20
Revision 4
Table 3-13 Summary of I/O Output Buffer Power (per pin)鈥擠efault I/O Software Settings1
CLOAD (pF)
VCCI (V)
Static Power
PDC8 (mW)2
Dynamic Power
PAC10 (W/MHz)3
Applicable to Pro I/O Banks
Single-Ended
3.3 V LVTTL/LVCMOS
35
3.3
鈥�
474.70
2.5 V LVCMOS
35
2.5
鈥�
270.73
1.8 V LVCMOS
35
1.8
鈥�
151.78
1.5 V LVCMOS (JESD8-11)
35
1.5
鈥�
104.55
3.3 V PCI
10
3.3
鈥�
204.61
3.3 V PCI-X
10
3.3
鈥�
204.61
Voltage-Referenced
3.3 V GTL
10
3.3
鈥�
24.08
2.5 V GTL
10
2.5
鈥�
13.52
3.3 V GTL+
10
3.3
鈥�
24.10
2.5 V GTL+
10
2.5
鈥�
13.54
HSTL (I)
20
1.5
7.08
26.22
HSTL (II)
20
1.5
13.88
27.22
SSTL2 (I)
30
2.5
16.69
105.56
SSTL2 (II)
30
2.5
25.91
116.60
SSTL3 (I)
30
3.3
26.02
114.87
SSTL3 (II)
30
3.3
42.21
131.76
Differential
LVDS
鈥�
2.5
7.70
89.62
LVPECL
鈥�
3.3
19.42
168.02
Applicable to Advanced I/O Banks
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
鈥�
468.67
2.5 V LVCMOS
35
2.5
鈥�
267.48
1.8 V LVCMOS
35
1.8
鈥�
149.46
1.5 V LVCMOS (JESD8-11)
35
1.5
鈥�
103.12
3.3 V PCI
10
3.3
鈥�
201.02
3.3 V PCI-X
10
3.3
鈥�
201.02
Notes:
1. Dynamic power consumption is given for standard load and software-default drive strength and output slew.
2. PDC8 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
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