Bus frequency (t<" />
參數(shù)資料
型號: TWR-S08PT60-KIT
廠商: Freescale Semiconductor
文件頁數(shù): 6/37頁
文件大?。?/td> 0K
描述: TOWER SYSTEM KIT S08PT60
標準包裝: 1
系列: S08
類型: MCU
適用于相關(guān)產(chǎn)品: Freescale 電源塔系統(tǒng)
所含物品: 4 個板,線纜,DVD
Switching specifications
5.2.1 Control timing
Table 5. Control timing
Num
C
Rating
Symbol
Min
Typical1
Max
Unit
1
P
Bus frequency (tcyc = 1/fBus)
fBus
DC
20
MHz
2
P
Internal low power oscillator frequency
fLPO
0.67
1.0
1.25
KHz
3
D
External reset pulse width2
textrst
1.5 ×
tSelf_reset
ns
4
D
Reset low drive
trstdrv
34 × tcyc
ns
5
D
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
tMSSU
500
ns
6
D
BKGD/MS hold time after issuing background
debug force reset to enter user or BDM modes3
tMSH
100
ns
7
D
IRQ pulse width
Asynchronous
tILIH
100
ns
D
Synchronous path4
tIHIL
1.5 × tcyc
ns
8
D
Keyboard interrupt pulse
width
Asynchronous
tILIH
100
ns
D
Synchronous path
tIHIL
1.5 × tcyc
ns
9
C
Port rise and fall time -
Normal drive strength
(HDRVE_PTXx = 0) (load
= 50 pF)5
tRise
10.2
ns
C
tFall
9.5
ns
C
Port rise and fall time -
Extreme high drive
strength (HDRVE_PTXx =
1) (load = 50 pF)5
tRise
5.4
ns
C
tFall
4.6
ns
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after
VDD rises above VLVD.
4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
textrst
RESET PIN
Figure 5. Reset timing
5.2
Switching specifications
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
14
Freescale Semiconductor, Inc.
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