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參數(shù)資料
| 型號(hào)： | TWO-CHIP |
| 英文描述： | High voltage fast-switching NPN power transistor |
| 中文描述： | 雙芯片的移動(dòng)處理器（117k解決方案） |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大小： | 117K |
| 代理商： | TWO-CHIP |
AN99-12
TWO CHIP SOLUTION FOR
MOBILE CPUs
2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
January 5, 2000
9
The comparator reference voltage positioning is such
that an increasing current sense voltage, VCS, i,e, an
elevating load current, causes the reference voltage to
decrease, and as a consequence, the core output volt-
age also droops. At no load current, there is no droop
while a maximum load, the droop is likewise maximum.
In order for the core voltage to be positioned around
the nominal V
voltage symmetrically and not just
one way downward from the nominal value, a DSPS
offset voltage, V
, can be introduced. The offset
voltage moves the comparator reference voltage up-
ward at no load. At optimal offsetting, the reference
voltage is above the nominal level for load currents
less than half of the maximum load, and below the
nominal value for currents higher than that. The maxi-
mum amount of core voltage positioning can be deter-
mined from the constrain which says the output voltage
at no load condition must still remain below the upper
threshold of the core voltage regulation window, and at
maximum load, it must be above the lower threshold.
The offset voltage can be generated across a resistor,
R
, which is also used to create the hysteresis voltage
by forcing a unipolar DSPS offsetting current through it.
The offsetting current is conveniently provided by a
high value resistor, R
, connected from the com-
parator CMP pin to the ground.
In DSPS hysterestic controller configuration, the com-
parator thresholds can be calculated from the DAC
voltage, V
, the DSPS offsetting voltage, V
,
the DSPS voltage V
, and the bipolar hysteresis
voltage, V
by summing them at the comparator in-
puts at the appropriate load current levels:
Core Voltage Offsetting
In order for the core voltage to be positioned around
the nominal V
voltage symmetrically and not just al-
ways one direction downward, a core offset voltage,
V
can be introduced. The offset voltage moves the
comparator reference voltage upwards. Using optimal
offsetting, the core comparator reference voltage will
be above the VID programmed nominal DAC voltage
for load currents less than half of the maximum load,
and below that for higher current. The maximum
amount of the core voltage positioning can be deter-
mined from the constraint that the output
voltage regu-
lation window, and at maximum load, it has to be
above the lower threshold.
The positioning offset voltage can be generated across
the same resistor, ROH also used to create the hys-
teresis voltage, by forcing a unipolar offsetting current
through it. The offsetting current is conveniently pro-
vided by a high value resistor, ROFFS connected from
the comparator CMP pin to the ground.
Current Limit Comparator
The current limit comparator monitors the core con-
verter output current and turns the high side switch off
when the current exceeds the upper current limit
threshold, VHCL and re-enable only if the load current
drops below the lower current limit threshold, VLCL.
The current is sensed by monitoring the voltage drop
across the current sense resistor, R
CS
, connected in
series with the core converter main inductor (the same
resistor used for DSPS input signal generation). The
thresholds have the following relationships:
DAC
OFFSET
OH
ROFFSET
ROH
,
VDAC
VCORE
,
VCORE
VCS
OFFSET
OH
CORE
V
CS
OH
DSPS
I
OH
DSPSOFFS
V
R
R
R
R
V
R
R
V
≈
+
+
=
=
<<
=
<<
REF
CLSET
CLOH
HCL
V
R
R
3
V
=
REF
CLSET
CLOH
LCL
V
R
R
2
V
=
REF
CLSET
CLOH
HYSCL
V
V
R
R
=
Roh
Rdac
Roffset
Rcore
)
Roh
Roffset
(
Rcore
sr
Re
sr
Re
Roh
Rdac
Roffset
Rcore
)
Roh
Roffset
(
Rcore
Vhys
2
:
Vcore
+
+
+
=
Roh
Rdac
Roffset
Rcore
)
Rdac
Rcore
(
Roffset
Icore
Rcs
Rcore
)
Roh
Roffset
(
Vdac
:
Vcore
+
+
=
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