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參數(shù)資料
| 型號： | TWO-CHIP |
| 英文描述： | High voltage fast-switching NPN power transistor |
| 中文描述： | 雙芯片的移動處理器（117k解決方案） |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 117K |
| 代理商： | TWO-CHIP |
AN99-12
TWO CHIP SOLUTION FOR
MOBILE CPUs
2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
January 5, 2000
10
Core Converter Soft Start Timer
The main purpose of this block is to control the ramp-
up time of the core voltage in order to reduce the initial
inrush current on the core input voltage (battery) rail.
The soft start circuit consists of an internal current
source, external soft start timing capacitor, internal
switch across the capacitor, and a comparator monitor-
ing the capacitor voltage.
LINEAR REGULATOR CONTROLLER
1.5V Linear Regulator
This block is a linear regulator controller, which drives
an external PNP bipolar transistor as a pass element.
The linear regulator is capable of delivering 500mA
steady state DC current and should support transient
current of 1A, assuming the output filtering capacitor is
properly selected to provide enough charge for the du-
ration of the load transient.
2.5V Linear Regulator
This block is a low drop-out (LDO) linear regulator con-
troller, which drives an external PNP bipolar transistor
as a pass element. The LDO linear regulator is capa-
ble of delivering 100mA steady DC current and should
support transient current of 100mA, assuming the out-
put filtering capacitor is properly selected to provide
enough charge for the duration of the load transient.
Linear Regulator Soft Start Timer
A soft start timer circuit of the linear regulators is simi-
lar to that of the core converter, and is used to control
the ramp up time of the linear regulator output volt-
ages. For maximum flexibility in controlling the start up
sequence, the soft start function of the linear regulators
is separated from that of the core converter.
VOLTAGE CLAMP
The level translator converts an input voltage swing on
the IO rail, into a voltage swing on the CLK or VCC rail
depending on where the open drain output of the trans-
lator is tied to through an external pull-up resistor. The
level translator has to track the input in phase, and
must be able to switch in 5ns (typical) following an in-
put threshold intercept.
APPLICATION INFORMATION
Power on/off Sequence
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