參數(shù)資料
型號(hào): TVP6000CPFP
廠(chǎng)商: TEXAS INSTRUMENTS INC
元件分類(lèi): 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL ENCODER, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù): 3/57頁(yè)
文件大?。?/td> 268K
代理商: TVP6000CPFP
1–5
1.6
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
RCM1
1
O
Programmable video vertical timing signal. For detailed programming information,
see the RCM_L21 register definition.
RCM2
3
I/O
Programmable video horizontal timing signal (can also be programmed for horizontal
active video signal. For detailed programming information, see RCM_L21 register
definition.
RCV1
2
I/O
Programmable video vertical timing signal. For programming infromation, see
SYN_CTRL0 register definition.
RCV2
4
I/O
Programmable video horizontal timing signal (can also be programmed for horizontal
active video signal). For detailed programming infromation, see SYN_CTRL0
register definition.
VREF
42
I/O
Test pin. VREF can be used for bandgap voltage output. For normal operation no
connection.
REFGND
45
Reference ground of output DACs. REFGND should be connected to AGND.
REFVDD
46
Reference power supply of the DACs. REFVDD should be connected to AVDD.
RES
9
I
Reset input, active low
SA
15
I
I2C slave address select
SCL
16
I/O
I2C serial clock input. Maximum clock rate of 400 kHz.
SDA
17
I/O
I2C serial data line
SDEN
11
I
Test pin. For normal applications connect to DGND.
TST
12
I
Test pin. For normal applications connect to DGND.
VP1[7:0]
69,71,72,
74,76–79
I
Y input port in 16-bit mode. For 8-bit multiplexed mode, VP1[7:0] is either the YUV
multiplexed port or should be left unconnected based on the FMT(2) register bit.
VP2[7:0]
53–60
I
UV input port in 16-bit mode. For 8-bit multiplexed mode, VP2[7:0] is either the YUV
multiplexed port or should be left unconnected based on the FMT(2) register bit.
VSUB
50
VSUB should be connected to AGND.
XDAC
64
I
XDAC sets the initial mode of operation for the output DACs immediately after reset. If
XDAC = GND the DACs will be in normal operation mode after reset. If XDAC = VDD,
the DACs will be in power down mode.
XTAL1
13
I
Crystal or oscillator input. CMOS input levels
XTAL2
14
I
Crystal input. Crystal is connected between XTAL1 and XTAL2.
Y
35
O
Luminance analog output signal for S-video output
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