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參數(shù)資料
| 型號(hào)： | TVP5154PNPRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK |
| 中文描述： | 4通道低功耗PAL / NTSC制式/ SECAM制式，帶有獨(dú)立的定標(biāo)器和視頻解碼器快速鎖定 |
| 文件頁數(shù)： | 9/78頁 |
| 文件大小： | 824K |
| 代理商： | TVP5154PNPRG4 |
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4.7 Timing Processor
4.8 VBI Data Processor
4.9 VBI FIFO and Ancillary Data in Video Stream
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A–MARCH 2006–REVISED JULY 2006
The timing processor is a combination of hardware and software running in the internal microprocessor
that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the
analog front end, and vertical sync detection.
The TVP5154 VBI data processor (VDP) slices various data services, such as teletext (WST, NABTS),
closed caption (CC), wide screen signaling (WSS), etc. These services are acquired by programming the
VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results
are stored in a FIFO only.
Table 4-1
lists a summary of the types of VBI data supported according to the
video standard. It supports ITU-R BT. 601 sampling for each.
Table 4-1. Data Types Supported by the VDP
LINE MODE REGISTER
(D0h–FCh) BITS [3:0]
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1111b
NAME
DESCRIPTION
WST SECAM
WST PAL B
WST PAL C
WST, NTSC B
NABTS, NTSC C
NABTS, NTSC D
CC, PAL
CC, NTSC
WSS, PAL
WSS, NTSC
VITC, PAL
VITC, NTSC
VPS, PAL
Active Video
Teletext, SECAM
Teletext, PAL, System B
Teletext, PAL, System C
Teletext, NTSC, System B
Teletext, NTSC, System C
Teletext, NTSC, System D (Japan)
Closed caption PAL
Closed caption NTSC
Wide-screen signal, PAL
Wide-screen signal, NTSC
Vertical interval timecode, PAL
Vertical interval timecode, NTSC
Video program system, PAL
Active video/full field
At power up, the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents
with the lookup table (see Section 9.2.63). This is done through port address C3h. Each read from or write
to this address auto increments an internal counter to the next RAM location. To access the VDP-CRAM,
the line mode registers (D0h–FCh) must be programmed with FFh to avoid a conflict with the internal
microprocessor and the VDP in both writing and reading. Full field mode must also be disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode.
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h–AFh,
both of which are available through the I
2
C port.
Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is
output during the horizontal blanking period following the line from which the data was retrieved.
Table 4-2
shows the header format and sequence of the ancillary data inserted into the video stream. This format is
also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can
store up to 11 lines of teletext data with the NTSC NABTS standard.
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Functional Description
9
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