參數(shù)資料
型號: TVP5154PNPRG4
廠商: Texas Instruments, Inc.
英文描述: 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK
中文描述: 4通道低功耗PAL / NTSC制式/ SECAM制式,帶有獨立的定標器和視頻解碼器快速鎖定
文件頁數(shù): 17/78頁
文件大?。?/td> 824K
代理商: TVP5154PNPRG4
www.ti.com
5.2.1
I
2
C Timing Requirements
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A–MARCH 2006–REVISED JULY 2006
Read Phase 1
abc
Step 1
I
2
C start (master)
0
S
Step 2
I
2
C general address (master)
7
1
6
0
5
1
4
1
3
1
2
0
1
X
0
0
Step 3
I
2
C acknowledge (slave)
9
A
Step 4
I
2
C read register address (master)
7
6
5
4
3
2
1
0
addr
addr
addr
addr
addr
addr
addr
addr
Step 5
I
2
C acknowledge (slave)
9
A
Step 6
I
2
C stop (master)
0
P
Read Phase 2
abc
Step 7
I
2
C start (master)
0
S
Step 8
I
2
C general address (master)
7
1
6
0
5
1
4
1
3
1
2
0
1
X
0
1
Step 9
I
2
C acknowledge (slave)
9
A
Step 10
I
2
C read data (slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Step 11
(1)
I
2
C not acknowledge (master)
9
A
Step 12
I
2
C stop (master)
0
P
(1)
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
The TVP5154 decoder requires delays in the I
2
C accesses to accommodate its internal processor’s timing.
In accordance with I
2
C specifications, the TVP5154 decoder holds the I
2
C clock line (SCL) low to indicate
the wait period to the I
2
C master. If the I
2
C master is not designed to check for the I
2
C clock line held-low
condition, the maximum delays must always be inserted where required. These delays are of variable
length; maximum delays are indicated in the following diagram:
Table 5-3. I
2
C Timing
Start
Slave address (B8h)
Ack
Subaddress
Ack
Data (XXh)
Ack
Wait 128
μ
s
(1)
Stop
(1)
If the SCL pin is not monitored by the master to enable pausing, a delay of 128
μ
s should be inserted between transactions for registers
00h through 8Fh.
Submit Documentation Feedback
17
I
2
C Host Interface
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