參數(shù)資料
型號(hào)： TVP5031PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 26/92頁(yè)
文件大小： 415K
代理商： TVP5031PFP
2–16
2.6
Host Interface
The host interface is used to initialize the internal microprocessor, to read and write status registers and control
registers, and to access sliced VBI data.
The interface modes supported by the TVP5031 are I2C, and three parallel interface modes. The host interface is
configured at powerup and reset using the GLCO, PALI, and the FID terminals as shown in Table 2–2.
Table 2–2. Host Port Mode Select
INTERFACE CONFIGURATION
TERMINALS
INTERFACE CONFIGURATION
GLCO
PALI
FID
I2C
0
1
Parallel A
1
0
1
Parallel B
1
0
Parallel C
1
NOTE: 1 = pullup
0 = pulldown
2.6.1
I2C Host Interface
The TVP5031 host interface is configured for I2C operation by attaching external pullup and pulldown resistors to the
GLCO, PALI, and FID terminals. The following is the combination of resistors required to select I2C host mode (1 is
pullup and 0 is pulldown).
GLCO
PALI
FID
I2C host port enabled
0
1
2.6.1.1 I2C Host Port Select
The I2C standard consists of two signals, serial input/output data line (VC1) and input/output clock line (VC0), which
carry information between the devices connected to the bus. A third signal (VC3) is used for slave address selection.
Although the I2C system can be multi-mastered, the TVP5031 will function as a slave device only.
Both SDA and SCL are bidirectional lines connected to a positive supply voltage via a pullup resistor. When the bus
is free, both lines are high.
The slave address select terminal (VC3) enables the use of two TVP5031 devices tied to the same I2C bus.
Table 2–3 summarizes the terminal functions of the I2C-mode host interface.
Table 2–3. I2C Host Port Terminal Description
SIGNAL
TYPE
DESCRIPTION
VC3 (I2CA)
I
Slave address selection
VC0 (SCL)
I/O (open drain)
Input/output clock line
VC1 (SDA)
I/O (open drain)
Input/output data line
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