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參數(shù)資料
| 型號(hào)： | TVP5022 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 36/91頁 |
| 文件大?。?/td> | 411K |
| 代理商： | TVP5022 |
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2–25
DC
Command
VC3
VC0
VC1
VC2
Wait
Address
Command
Slave Termination
Figure 2–25. Functional Timing Example of Slave Termination
VIP Configuration Register:
The TVP5022 supports VIP configuration registers that are accessible only in the VIP host mode.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(from TV5020)
7
6
5 4 3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VIP Config. Register read
0
1
1 0 0
0
A A A A A A A A D D D D D D D D
General TVP5022 Registers:
The bulk of the TVP5022 register space consists of status and control registers that are available to the I2C,
VIP, and VMI host modes.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(from TV5020)
7
6
5 4 3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
General TVP register read
0
1
1 0 0
0
1
A A A A A A A A D D D D D D D D
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(to TV5020)
7
6
5 4 3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
General TVP register write
0
1
0 0 0
0
1
A A A A A A A A D D D D D D D D
2.7.3.2
No-latency Read
No-latency read eliminates the extended wait states of normal read operations. No latency read consists
of two zero-wait state phases separated by an idle period during which the host may perform other
operations. The first phase identifies the register address to be read. This will be stored in an intermediate
data buffer. The current data in the intermediate data buffer is immediately read out. This information is to
be ignored because it is invalid data.
Following the completion of the first phase, the host must wait for at least 64
s to ensure that the data
requested in the first phase is stored in the intermediate data buffer. The host initiates the second phase
of the read by reading the data from the intermediate data buffer.
No Latency Read Phase 1:
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(from TV5020)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No latency read
phase 1
0
1
0
1
0 A A A A A A A A
du
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