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參數(shù)資料
| 型號： | TVP5022 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 25/91頁 |
| 文件大小： | 411K |
| 代理商： | TVP5022 |
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2–15
into a wait state. Data transfer continues when the slave is ready for another byte of data and releases the
clock line (SCL).
Data transfer with acknowledge is necessary. The master generates an acknowledge related clock pulse.
The master releases the SDA line high during the acknowledge clock pulse. The slave pulls down the SDA
line during the acknowledge clock pulse so that it remains stable low during the high period of this clock
pulse.
When a slave does not acknowledge the slave address, the data line is left high. The master then generates
a stop condition to abort the transfer.
If a slave acknowledges the slave address, but some time later in the transfer cannot receive any more data
bytes, the master again aborts the transfer. The slave indicates a not ready condition by generating the not
acknowledge. The slave leaves the data line high and the master generates the stop condition.
If a master-receiver is involved in a transfer, it indicates the end of data to the slave-transmitter by not
generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must
release the data line to allow the master to generate a stop or repeated start condition.
2.6.2
I2C Write Operation
Data transfers occur using the following illustrated formats.
The I2C master initiates a write operation to the TVP5022 by generating a start condition followed by the
TVP5022’s I2C address (101110X). The address is in MSB first bit order followed by a 0 to indicate a write
cycle. After receiving a TVP5022 acknowledge, the I2C master sends a subaddress of the register or the
block of registers where it will write. Following the subaddress is one or more bytes of data, with MSB first.
The TVP5022 acknowledges the receipt of each byte upon completion of each transfer. The I2C master ends
a write operation by generating a stop condition.
The X in the address of the TVP5022 is 0 when the I2CA terminal is low and the X is 1 when the I2CA is high.
If the read or write cycle contains more than one byte, the internal subaddress does not increment
automatically.
0
I2C Start (Master)
S
7
6
5
4
3
2
1
0
I2C General address (Master)
1
0
1
0
X
0
9
I2C Acknowledge (Slave)
A
7
6
5
4
3
2
1
0
I2C Write register address (Master)
Addr
9
I2C Acknowledge (Slave)
A
7
6
5
4
3
2
1
0
I2C Write data (Master)
Data
9
I2C Acknowledge (Slave)
A
0
I2C Stop (Master)
P
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5031 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
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| TVP5031TQFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5040 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL Digital Video Decoder With Macrovision Detection |
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