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參數(shù)資料
| 型號： | TVP3409-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| 中文描述： | 先進(jìn)的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS） |
| 文件頁數(shù)： | 19/57頁 |
| 文件大?。?/td> | 312K |
| 代理商： | TVP3409-135 |
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2–7
2.2.8
Control register 1 is operational on power up. The control register can be read from or written to by the MPU
at any time and is not initialized. All bits are set to 0 upon asserting RESET. To read or write this register,
set bit CR0(0) = 1, write 0x05 to the WMA, and set RS(1,0) = 10. This register can be accessed by using
indexed addressing (see Table 2–4). Table 2–9 defines the bits of the control register.
Control Register 1 (CR1)
CR1(4) enables the blank pedestal.
CR1(3) powers down clock synthesizer A.
CR1(2) powers down clock synthesizer B.
CR1(1) disables the SENSE terminal.
CR1(0) is reserved. Bit 0 always returns a 0 regardless of what value is written. CR1(0) is the LSB and
corresponds to D0 on the MPU port.
Table 2–9. Control Register 1
BIT
NAME
DESCRIPTION
CR1(7)
Reserved
CR1(6,5)
Reserved
CR1(4)
Blank
Pedestal
Enable
Logic 0: No blank pedestal.
Logic 1: Blank pedestal enabled.
CR1(4) controls whether the BLANK terminal shuts off a 7.5 IRE current source on
R, G, and B when blanking is asserted. For VGA compatibility, write a 0 to bit 4.
CR1(3)
OTCLKA
Synthesizer
Power
Down
Logic 0: OTCLKA synthesizer enabled.
Logic 1: OTCLKA synthesizer powered down and output is 3-stated.
A logic 1 disables clock synthesizer A (PLLA). This bit should be a logic 1 to achieve
the lowest power state for the device. Set this bit to a logic 1 when not using clock
synthesizer A.
CR1(2)
OTCLKB
Synthesizer
Power
Down
Logic 0: OTCLKB synthesizer enabled.
Logic 1: OTCLKB synthesizer powered down and output is 3-stated.
A logic 1 disables clock synthesizer B (PLLB). Bit 2 should be a logic 1 to achieve
the lowest power state for the device. Set bit 2 to a logic 1 when not using clock
synthesizer B.
CR1(1)
SENSE
Disable
Logic 0: SENSE terminal enabled.
Logic 1: SENSE terminal disabled and output is 3-stated.
A logic 0 enables the SENSE terminal to output the SENSE signal.
CR1(0)
Institute of Radio Engineers (IRE)
Reserved
This bit always returns a 0 without regard to what was written.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3409-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3409-170CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3703 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
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