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參數(shù)資料
| 型號： | TVP3409-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| 中文描述： | 先進(jìn)的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS） |
| 文件頁數(shù)： | 11/57頁 |
| 文件大小： | 312K |
| 代理商： | TVP3409-135 |
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1–5
1.7
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BLANK
7
I
Blank (active low, TTL compatible). BLANK is latched on the rising edge of PCLK. When
BLANK is low, the 1.44 mA current source on the analog outputs is turned off. The DACs
ignore digital input from memory. In mode 14, pixel data is aligned with the rising edge
of PCLK after BLANK rises.
Compensation terminal. Bypass this terminal with an external 0.1
μ
F capacitor to VCC.
Data bus (TTL compatible). Data is transferred between the data bus and the internal
registers under control of the RD and WR signals. In a microprocessor unit (MPU) write
operation, D(7–0) is latched on the rising edge of WR. To read data D(7–0) from the
device, RD must be in an active low state. The rising edge of the RD signal indicates the
end of a read cycle. Following the read cycle, the data bus goes to a high-impedance
state. Note that for 6-bit operation, color data is contained in the lower six bits of the data
bus. D0 is the LSB and D5 is the MSB. When the MPU writes color data, D6 and D7 are
ignored. During MPU read cycles, D6 and D7 are a logic 0.
COMP
45
D(7–0)
14–21
I/O
FS(1,0)
2, 3
I
Clock frequency select (TTL compatible). FS(1,0) select the register sets that determine
the frequency of the clock synthesizers. FS(1,0) select the register sets when CC0(7)
and CC0(3) = 0. When CC0(7) and CC0(3) = 1, bits in the CC register select the register
sets.
GND
10, 26,
36, 39,
44, 47,
60
Ground. GND terminals connect to circuit ground.
OTCLKA
8
O
Output clock A (TTL compatible). Output clock from analog PLLA synthesizer.
OTCLKB
11
O
Output clock B (TTL compatible). Output clock from analog PLLB synthesizer.
PCLK
59
I
Pixel clock (TTL compatible). The duty cycle can be 30% to 70%. The rising edge of the
pixel clock latches the pixels and the BLANK input.
P(12–13),
P(14–15),
P(0–7),
P(8–11)
1,4,
12,13,
51–58,
64–67
I
Pixel in (TTL compatible). These terminals are latched on the rising edge of PCLK. Pixels
are presented to the DACs as color data in true-color modes and are used as addresses
in the pseudocolor mode to look up color data in the color RAM. Unused inputs should
be connected to GND.
RD
5
I
Read (active low, TTL compatible). When RD is low, data is transfered from the selected
internal register to the data bus. RS(1,0) is latched on the falling edge of RD.
RED,
GREEN,
BLUE
37,
38,
40
O
Color analog out. High-impedance current sources that are capable of driving a
double-terminated 75-
coaxial cable.
REF
46
Voltage reference. REF should be bypassed with an external 0.1
μ
F capacitor to GND.
Reset (TTL compatible). This input resets internal registers to 0x00. RESET programs
the clock synthesizer register sets to produce 28.322 MHz and 25.175 MHz.
RESET
62
I
RSET
42
I
Reference resistor. An external resistor (RSET) is connected between the RSET terminal
and GND to control the magnitude of the full-scale current (refer to Section 2.6.8, DAC
Gain for more information).
RS(1,0)
23, 24
I
Register select (TTL compatible). These inputs are sampled on the falling edge of RD
or WR to determine which one of the internal registers is to be accessed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3409-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3409-170CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3703 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
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