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參數(shù)資料
| 型號： | TVP3026-220APCE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 91/107頁 |
| 文件大?。?/td> | 513K |
| 代理商： | TVP3026-220APCE |
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B–1
Appendix B
PLL Programming Examples
Loop Clock PLL
The internal structure of the loop clock PLL is shown in Figure B–1. The loop clock PLL phase aligns the
received LCLK with the internal dot clock in order to ensure reliable data latching into the TVP3026. The
phase detector performs phase comparison at the rising edge of the received clocks after the N and M
prescalers. The charge pump and loop filter generate an analog control signal to the voltage controlled
oscillator. The VCO frequency is then divided by the P and Q post-scalers. The P post-scaler provides
division ratios of 1, 2, 4, or 8. The Q post-scalar provides additional division ratios of 2, 4, 6, 8, 10, 12, 14
and 16. The Q post-scalar provides for the extra low frequencies needed for low-resolution graphics using
a high multiplex ratio, such as 640 x 480, 8 bits/pixel, using a 64-bit pixel bus. The output from the loop clock
PLL or the pixel clock PLL may be selected for output on the RCLK terminal.
1
65–N
Phase
Detector
1
65–M
Charge
Pump
VCO
1
2P
1
2(Q+1)
OUT
Dot Clock
LCLK
Up
Down
Figure B–1. Loop Clock PLL Structure
As a programming example, we can follow the procedure of subsection 2.4.3.1, Programming for All Modes
Except Packed-24 for a mode using a 170 MHz pixel clock, 8 bits/pixel, a 64-bit pixel bus, and an external
division factor (through the GUI accelerator) of 2.
FD
170 MHz,
B
8,
W
64,
K
2
FL
FD
B
W
170
8
64
21.25 MHz
FR
K
FL
2
21.25
42.5 MHz
N
65
4
W
B
65
4
64
8
33
0x21
M
61
0x3D
Z
27.5
(65
N)
FD
K
27.5
(65
33)
170
2
2.59
Since Z < 16 and log
2
(Z) is between 1 and 2, then P = 1 and Q = 0
Since bits 7 and 6 of the N-value register must be 1,1 the N-value register is loaded with 0x21 + 0xC0 = 0xE1.
The M-value register is loaded with 0x3D. Since bits 7–2 of the P-value register must be 1111 00, the P-value
register is loaded with 0x01 + 0xF0 = 0xF1. Bits 2–0 of the MCLK/loop clock control register (index: 0x39)
are loaded with the Q value of 000.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3026-220BMDN | Video Interface Palette |
| TVP3026-250AMDN | Video Interface Palette |
| TVP3026-250APCE | Video Interface Palette |
| TVP3026-250BMDN | Video Interface Palette |
| TVP3026-135AMDN | Video Interface Palette |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-220BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026-220PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-230CPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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