參數(shù)資料
型號(hào)： TVP3026-135
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器）
文件頁(yè)數(shù)： 21/107頁(yè)
文件大?。?/td> 707K
代理商： TVP3026-135
2–7
Table 2–7. PLL Top Level Registers
INDEX
REGISTER
0x2C
PLL address register (PAR)
0x2D
Pixel clock PLL data register (PPD)
0x2E
MCLK PLL data register (MPD)
0x2F
Loop clock PLL data register (LPD)
The PLL address register (PAR) points to the M, N, P, and status registers of each PLL. This register allows
read and write access and contains three 2-bit pointers, one for each PLL, according to the Table 2–8. Each
pointer may be programmed independently.
Table 2–8. PLL Address Register
(Index: 0x2C, Access: R/W, Default: Uninitialized)
PAR BITS
POINTER
1–0
Pixel clock PLL data register pointer
3–2
MCLK PLL data register pointer
5–4
Loop clock PLL data register pointer
Each PLL data register pointer directs its associated PLL to one of its four PLL registers according to
Table 2–9.
Table 2–9. PLL Data Register Pointer Format
BIT 1
BIT 0
REGISTER
0
0
N-value register
0
1
M-value register
1
0
P-value register
1
1
Status register (read-only)
Once the PLL data register pointers are set, the selected register is accessed through the pixel clock PLL
data register (index: 0x2D), MCLK PLL data register (index: 0x2E) or the loop clock PLL data register (index:
0x2F). The PLL data register pointer bits are independently autoincremented following a write cycle to the
corresponding PLL data register. The current state of each pointer can be identified by reading the PLL
address register (index: 0x2C). The PLL data register pointer bits do not autoincrement following a read
cycle of the PLL data registers.
The most efficient way to program the pixel clock PLL is to first write zeros to PLL address register bits
PAR(1,0) followed by three consecutive writes to the pixel clock PLL data register to program the N, M, and
P-value registers. Following the third write, the pixel clock PLL pointer will point to the read-only status
register. The status register can then be polled until the LOCK bit is set (the pointer does not autoincrement
on reads). For test purposes, the pixel clock PLL can be output on the PCLKOUT terminal by setting the
pixel clock PLL P-value register bit 6 to 1.
相關(guān)PDF資料
PDF描述
TVP3026-175 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TVP3026-175M Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TVP3026-220 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TVP3026-250 Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
TX24 60.8 MM 5 X 8 DOT MATRIX DISPLAYS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3026-135AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135APCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135BMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135BPCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135MDN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
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