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參數(shù)資料
| 型號： | tua 6110 |
| 廠商： | SIEMENS AG |
| 英文描述： | SAT Mixer-Oscillator-PLL(衛(wèi)星混頻器-振蕩器-鎖相環(huán)電路) |
| 中文描述： | 稅務(wù)總局攪拌機振蕩器鎖相環(huán)（衛(wèi)星混頻器-振蕩器-鎖相環(huán)電路） |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 458K |
| 代理商： | TUA 6110 |
Data Sheet
TUA6110XS
Wireless Group
7
16.6.99
9.3
Data is exchanged between the processor and the PLL via the I
2
C bus. The clock is generated by the proces-
sor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open
collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance
the noise immunity of the I
2
C bus.
I
2
C-Bus Interface
The data from the processor pass through an I
2
C bus controller. Depending on their function the data are sub-
sequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH).
Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes
LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further infor-
mation transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive
clock edge.
The table 1 ”bit allocation” should be referred to the following description. All telegrams are transmitted byte-
by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowl-
edge condition). The first byte is comprised of seven address bits. These are used by the processor to select
the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are
written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte deter-
mines whether a divider ratio or control information is to follow. In each case the second byte of the same data
type has to follow the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the
status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; oth-
erwise the data line is released to allow the processor to generate a stop condition. The status word consists
of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag.
Three different chip addresses can be set by appropriate connection of pin CAS (see table 2 ”address
selection”).
When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to
LOW, which would block the bus. The power-on reset flag POR is set at power-on and if V
VCCD
falls below
3.2 V. It will be reset at the end of a READ operation.
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