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參數(shù)資料
| 型號： | tua 6110 |
| 廠商： | SIEMENS AG |
| 英文描述： | SAT Mixer-Oscillator-PLL(衛(wèi)星混頻器-振蕩器-鎖相環(huán)電路) |
| 中文描述： | 稅務總局攪拌機振蕩器鎖相環(huán)（衛(wèi)星混頻器-振蕩器-鎖相環(huán)電路） |
| 文件頁數(shù)： | 10/26頁 |
| 文件大小： | 458K |
| 代理商： | TUA 6110 |
Data Sheet
TUA6110XS
Wireless Group
6
16.6.99
9
Circuit Description
9.1
The mixer-oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators
for Band A/Band and a reference voltage source.
Mixer-Oscillator block
In a complete tuner the input signal passes a frontend stage with MESFET amplifier, a double-tuned band-
pass filter and is then fed to the balanced mixer input of the IC which has a low-impedance input.
The input signal is mixed there with the on chip oscillator signal.
9.2
The mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential signal at the programmable
divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through
32767 and is then compared in a digital frequency / phase detector to a reference frequency f
ref
= 125 kHz.
This frequency is derived from a balanced, low-impedance 4 MHz crystal oscillator (pin Q, Qx) divided by
Q = 32.
PLL block
The phase detector has two outputs UP and DOWN that drive two current sources I+ and I- of a charge pump.
If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the
I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pul-
ses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state
(PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the
VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output
is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however,
that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in
the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments.
If the VCO is not working the PLL locks to a tuning voltage of 33V.
By means of control bit 5I the pump current can be switched between two values by software. This program-
mability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO
gains can be compensated, for example.
The software-switched ports P0, P1, P2 are general-purpose open-collector outputs. The test bit T1 = 1,
switches the test signals f
ref
(4 MHz / 32) and C
y
(divided input signal) to P0 and P1 respectively. P0, P1, P2
are bidirectional.
The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the
period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input fre-
quency from the programmed frequency is given by
f =
±
I
P
(K
VCO
/ f
Q
) (C
1
+C
2
) / (C
1
C
2
)
where I
P
is the charge pump current, K
VCO
the VCO gain, f
Q
the crystal oscillator frequency and C
1
, C
2
the
capacitances in the loop filter (see application circuit). As the charge pump pulses at 125 kHz (= f
ref
), it takes
a maximum of 16
μ
s for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive
f
ref
periods. Therefore it takes between 128 and 144
μ
s for FL to be set after the loop regains lock.
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