參數(shù)資料
型號(hào)： tua 4401
廠商： SIEMENS AG
英文描述： FM Car Radio IC with PLL(FM車載電臺(tái)芯片(帶鎖相環(huán)))
中文描述： 汽車調(diào)頻收音機(jī)芯片（調(diào)頻車載電臺(tái)芯片（帶鎖相環(huán)）與鎖相環(huán)）
文件頁(yè)數(shù)： 15/32頁(yè)
文件大小： 618K
代理商： TUA 4401
Specification
TUA 4401
Semiconductor Group
16
1.6.99
8.7
Crystal oscillator
A master crystal oscillator provides all necessary clock frequencies for the whole IC. A 61.5 MHz
crystal is used in 3rd harmonic mode.
The oscillator frequency can fine tuned with a serial bus controlled 4 bit D/A converter.
The crystal frequency is used as reference frequency for the PLL oscillator and IF counter. It is also
used as clock for the ADC’s. Finally the crystal frequency divided by 6 (10.25 MHz) is
available at a pin as low pass filtered voltage, it can be disabled with the serial bus.
8.8
Output ports
PORT_1 / 2 are NMOS Open drain outputs.
8.9
SOCCAR Bus
The TUA4401 supports the I
2
C bus protocol (2 wire) or 3 Wire bus protocol (3 or 4 wire) operation
selectable by pin 4: BUS_MODE (I
2
C=low, 3W=high). All bus pins ( BUS_MODE, SCL, SDA,
BUS_ENA) are Schmitt-triggered input buffer for 3V or 5V
μ
C.
The bit stream begins with the most significant bit (MSB), is shifted in (write mode) on the low to
high transition of CLK and is shifted out (read mode) on the high to low transition of CLK.
I
2
C bus mode
In this mode pin4 (BUS_MODE) = low and pin8 (BUS_ENA)=low. In this mode SDA is a bidirectional
input / output pin.
Data Transition:
Data transition on the pin SDA must only occur when the clock SCL is low. SDA transitions while
SCL is high will be interpreted as start or stop condition.
Start Condition (STA):
A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high
level.This start condition must precede any command and initiate a data transfer onto the bus.
Stop Condition (STO):
A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable
high level. This condition terminate the communication between the devices and forces the bus
interface into the initial conditions.
Acknowlage (ACK):
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has receive the
8 bits of data correctly.
Data Transfer Write Mode:
To start the communication, the bus master must initiate a start condition, followed by the 8bit chip
address (write). The chip address for the TUA 4401 is fixed as ”1100110” (MSB at first). The last bit
(LSB=A0) of the chip address byte defines the typ of operation to be performed:
A0=1, a read operation is selected and A0=0, a write operation is selected. After this comparision
the TUA 4401 will generate an ACK.
After this device addressing the desired sub address byte and data bytes must be followed. The
subaddresses determines which one of the 9 data bytes (00H...07H,0BH) is transmitted first. At the end
of data transition the master must be generate the stop condition.
Data Transfer Read Mode:
To start the communication in the read mode, the bus master must initiate a start condition, followed
by the 8bit chip address (write: A0=0), followed by the sub address read (82H or 83H), followed by
the chip address (read: A0=1). After that procedure the 16bit data register 82H or the 8bit data
register 83H is read out. After the first 8 bit read out, the uP mandatory send LOW during the
ACK-clock. After the second 8 bit read out the uP mandatory send HIGH during the ACK-clock.
At the end of data transition the master must be generate the stop condition.
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相關(guān)代理商/技術(shù)參數(shù)
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