參數(shù)資料
型號(hào)： TSS901ESASL3
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, QFP196
封裝： MQFP-196
文件頁數(shù)： 24/28頁
文件大?。?/td> 601K
代理商： TSS901ESASL3
5
Rev. B - July 29, 1999
TSS901E
1.5 PPU Functional Description
Since the Protocol Processing Unit (PPU) determines a major part of the TSS901E functionality, the principal
blocks of the PPU and their function are described here. This functionality is provided for every DS link channel
of the TSS901E.
q
Protocol Execution Unit: This unit serves as the main controller of the PPU block. It receives the tokens from
the DS macrocell and interprets (in protocol mode) the four header data characters received after an EOP1/
EOP2 control character. If the address field matches the link channel address and the command field contains
a valid command then forwarding of data into the receive FIFO is enabled. If the command field contains a
"simple control command" then the execution request is forwarded to the command execution unit.
The protocol execution unit also enables forwarding of header data characters to the acknowledge generator
and provides an error signal in case of address mismatch, wrong commands or disabled safety critical "simple
control commands".
The protocol execution unit is disabled in "transparent" or “wormhole routing” operation mode.
q
Receive, Transmit, Acknowledge: The transmit and receive FIFOs decouple the DS link related operations
from the TSS901E related operations in all modes and such allows to keep the speed of the different units
even when the source or sink of data is temporarily blocked.
In the protocol mode a further FIFO (acknowledge FIFO) is used to decouple sending of acknowledges from
receiving new data when the transmit path is currently occupied by a running packet transmission.
q
Command Execution Unit: This unit performs activating resp. deactivating of the CPU reset and the specific
external signals and provides the capability to reset one or all links inside the TSS901E, all actions requested
by the decoded commands from the protocol execution unit.
The unit contains a register controlling the enable/disable state of safety critical commands which is set into
the 'enable' state upon command request and which is reset after a safety critical command has been executed.
The CPU reset and the specific external signals are forwarded to the Protocol Command Interface (PRCI).
1.6 Fault Tolerance
The IEEE Std 1355-1995 specifies low level checks as link disconnect detection and parity check at token level.
The TSS901E provides, through the Protocol Processing Unit, features to reset a link or all links inside the TSS901E,
to reset the local CPU or to send special signals to the CPU commanded via the links.
Additionally it is possible to enable a checksum coder/decoder to have fault detection capabilities at packet level.
相關(guān)PDF資料
PDF描述
TSSH-106-01-L-D 12 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER
TSSH-108-01-T-DV 16 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT
TSSH-112-01-S-D 24 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER
TSSH-113-01-L-DV-LC-M 26 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT
TSSH-117-01-S-DV-LC 34 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT
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